In preparation for adding a C3600 machine with 40 bits of physical address space, and moving C3700 to 44 bits, a CPU model configuration struct is added to HPPACPUClass.
Two fields are added describing the size of the physical address space, and whether or not the CPU uses the PA-RISC 2.0 architecture. The latter was previously a field in CPUHPPAState. phys_addr_bits is currently set but unused, and will be used in the following commit. Signed-off-by: Anton Johansson <[email protected]> --- target/hppa/cpu.h | 24 ++++++++++++++++++++---- target/hppa/cpu.c | 27 +++++++++++++++++++-------- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 092e647ccf..43b4882fb4 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -270,8 +270,6 @@ typedef struct CPUArchState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - bool is_pa20; - target_ulong kernel_entry; /* Linux kernel was loaded here */ target_ulong cmdline_or_bootorder; target_ulong initrd_base, initrd_end; @@ -290,6 +288,18 @@ struct ArchCPU { QEMUTimer *alarm_timer; }; +/** + * HPPACPUDef: + * @phys_addr_bits: Number of bits in the physical address space. + * @is_pa20: Whether the CPU model follows the PA-RISC 2.0 or 1.1 spec. + * + * Configuration options for a HPPA CPU model. + */ +typedef struct HPPACPUDef { + uint8_t phys_addr_bits; + bool is_pa20; +} HPPACPUDef; + /** * HPPACPUClass: * @parent_realize: The parent class' realize handler. @@ -302,11 +312,17 @@ struct HPPACPUClass { DeviceRealize parent_realize; ResettablePhases parent_phases; + const HPPACPUDef *def; }; -static inline bool hppa_is_pa20(const CPUHPPAState *env) +static inline const HPPACPUDef *hppa_def(CPUHPPAState *env) +{ + return HPPA_CPU_GET_CLASS(env_cpu(env))->def; +} + +static inline bool hppa_is_pa20(CPUHPPAState *env) { - return env->is_pa20; + return hppa_def(env)->is_pa20; } static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c8079016bf..1ba281df20 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -203,13 +203,6 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) tcg_cflags_set(cs, CF_PCREL); } -static void hppa_cpu_initfn(Object *obj) -{ - CPUHPPAState *env = cpu_env(CPU(obj)); - - env->is_pa20 = !!object_dynamic_cast(obj, TYPE_HPPA64_CPU_PA_8700); -} - static void hppa_cpu_reset_hold(Object *obj, ResetType type) { HPPACPUClass *scc = HPPA_CPU_GET_CLASS(obj); @@ -284,6 +277,16 @@ static const TCGCPUOps hppa_tcg_ops = { #endif /* !CONFIG_USER_ONLY */ }; +static void hppa_cpu_class_base_init(ObjectClass *oc, const void *data) +{ + HPPACPUClass *acc = HPPA_CPU_CLASS(oc); + /* Make sure all CPU models define a HPPACPUDef */ + g_assert(!object_class_is_abstract(oc) && data != NULL); + if (data) { + acc->def = data; + } +} + static void hppa_cpu_class_init(ObjectClass *oc, const void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -318,18 +321,26 @@ static const TypeInfo hppa_cpu_type_infos[] = { .parent = TYPE_CPU, .instance_size = sizeof(HPPACPU), .instance_align = __alignof(HPPACPU), - .instance_init = hppa_cpu_initfn, .abstract = true, .class_size = sizeof(HPPACPUClass), .class_init = hppa_cpu_class_init, + .class_base_init = hppa_cpu_class_base_init, }, { .name = TYPE_HPPA_CPU_PA_7300LC, .parent = TYPE_HPPA_CPU, + .class_data = &(const HPPACPUDef) { + .phys_addr_bits = 32, + .is_pa20 = false, + }, }, { .name = TYPE_HPPA_CPU_PA_8700, .parent = TYPE_HPPA_CPU, + .class_data = &(const HPPACPUDef) { + .phys_addr_bits = 40, + .is_pa20 = true, + }, }, }; -- 2.52.0
