On 2/10/26 14:27, Thomas Huth wrote:
On 04/02/2026 13.07, Ilya Leoshkevich wrote:
v3:
https://lore.kernel.org/qemu-devel/[email protected]/
v3 -> v4: Use parts_round_to_int_normal() (Richard).
Drop saved_flags.
Collect R-bs (Thomas, Richard).
v2:
https://lore.kernel.org/qemu-devel/[email protected]/
v2 -> v3: Use FloatParts64 (Richard).
Improve "smallish" comment (Richard).
Use parts_muladd_scalbn (Richard).
Get rid of manual precision rounding (Richard).
New patch: parts_round_to_int_normal() improvement.
New 64-bit testcase for a fuzzer finding on one of the
intermediate versions. I have to admit I did not put down and
then forgot what exactly it was about, but it must be
interesting, so I decided to keep it.
v1:
https://lore.kernel.org/qemu-devel/[email protected]/
v1 -> v2: Move the implementatation to fpu/ and rewrite using
FloatParts (Richard). I can't say I particularly like the way
it looks, but at least most macros are gone and it survives
fuzzing.
Explain why we need -O0 for the test (Alex).
New patch: s390_get_bfp_rounding_mode().
Add a few comments with calculation examples to the test.
Hi,
This series implements DIVIDE TO INTEGER instruction, which is
required to run LuaJIT.
Patch 1 is a debugging helper, patch 2 is a small refactoring, patch 3
is an improvement for an FPU rounding helper, patch 4 is the
implementation.
Since the instruction is quite complex, I've extensively tested it
using a libFuzzer-based harness [1] that compares emulation with native
execution at ~15k exec/s. The tests (patch 5) use data generated
this way.
Best regards,
Ilya
[1] https://gitlab.com/iii-i/qemu/-/tags/iii/wip/fuzz-tcg/v2
Ilya Leoshkevich (5):
target/s390x: Dump Floating-Point-Control Register
target/s390x: Extract s390_get_bfp_rounding_mode()
fpu: Restrict parts_round_to_int_normal to target precision
target/s390x: Implement DIVIDE TO INTEGER
tests/tcg/s390x: Test DIVIDE TO INTEGER
fpu/softfloat-parts.c.inc | 7 +-
fpu/softfloat.c | 142 +++++++++++++++
Hi Ilya,
I'm sorry, but this seems to trigger a failure in the CI (when
undefined behaviour sanitizers are enabled):
https://gitlab.com/thuth/qemu/-/jobs/13055886506
Could you please have a look?
Thanks,
Thomas
Thanks for the report!
Apparently I should not have removed "& 63" in 3/5.
For FloatParts64 it's a no-op.
For FloatParts128 it's a no-op, unless rounding is in the low word, and
that's what the sanitizer has flagged.
For example, if N == 128, exp == 128, frac_size == 126, the value is
already an integer (exp >= frac_size), but we still want to zero out the
last bit.
So frac_lsb needs to be DECOMPOSED_IMPLICIT_BIT >> (126 & 63).
"& 63" converts the true bit offset to the bit offset within frac_lo.
I will restore it.
