On 2/11/2026 3:05 AM, Chen, Zide wrote:
>
> On 2/9/2026 11:30 PM, Mi, Dapeng wrote:
>> On 1/29/2026 7:09 AM, Zide Chen wrote:
>>> When PMU is disabled, guest CPUID must not advertise Debug Store
>>> support. Clear both CPUID.01H:EDX[21] (DS) and CPUID.01H:ECX[2]
>>> (DS64) in this case.
>>>
>>> Set IA32_MISC_ENABLE[12] (PEBS_UNAVAILABLE) when Debug Store is not
>>> exposed to the guest.
>>>
>>> Note: Do not infer that PEBS is unsupported from
>>> IA32_PERF_CAPABILITIES[11:8] (PEBS_FMT) being 0. A value of 0 is a
>>> valid PEBS record format on some CPUs.
>>>
>>> Signed-off-by: Zide Chen <[email protected]>
>>> ---
>>> V2:
>>> - New patch.
>>>
>>> target/i386/cpu.c | 6 ++++++
>>> target/i386/cpu.h | 1 +
>>> 2 files changed, 7 insertions(+)
>>>
>>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>>> index ec6f49916de3..445361ab7a06 100644
>>> --- a/target/i386/cpu.c
>>> +++ b/target/i386/cpu.c
>>> @@ -9180,6 +9180,10 @@ static void x86_cpu_reset_hold(Object *obj,
>>> ResetType type)
>>> env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
>>> }
>>>
>>> + if (!(env->features[FEAT_1_EDX] & CPUID_DTS)) {
>>> + env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
>>> + }
>>> +
>>> memset(env->dr, 0, sizeof(env->dr));
>>> env->dr[6] = DR6_FIXED_1;
>>> env->dr[7] = DR7_FIXED_1;
>>> @@ -9474,6 +9478,8 @@ void x86_cpu_expand_features(X86CPU *cpu, Error
>>> **errp)
>>> env->features[FEAT_1_ECX] &= ~CPUID_EXT_PDCM;
>>> }
>>>
>>> + env->features[FEAT_1_ECX] &= ~CPUID_EXT_DTES64;
>>> + env->features[FEAT_1_EDX] &= ~CPUID_DTS;
>> Strictly speaking, we need to check BTS as well before clearing DS. BTS
>> also depends on DS.
> But BTS is already unconditionally disabled from the guest in patch 1/11.
Yes, but from code logic, it's incomplete. We need to check both PEBS and
BTS are unavailable, and then disable DS.
>
>
>>> env->features[FEAT_7_0_EDX] &= ~CPUID_7_0_EDX_ARCH_LBR;
>>> }
>>>
>>> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
>>> index 5ab107dfa29f..0fecf561173e 100644
>>> --- a/target/i386/cpu.h
>>> +++ b/target/i386/cpu.h
>>> @@ -483,6 +483,7 @@ typedef enum X86Seg {
>>> /* Indicates good rep/movs microcode on some processors: */
>>> #define MSR_IA32_MISC_ENABLE_FASTSTRING (1ULL << 0)
>>> #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11)
>>> +#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12)
>>> #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
>>> #define MSR_IA32_MISC_ENABLE_DEFAULT (MSR_IA32_MISC_ENABLE_FASTSTRING
>>> |\
>>> MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)
