From: Ruslan Ruslichenko <[email protected]> This patch implements the FDTGenericIntc interface for the ARM GICv3 interrupt controller.
This enables the generic FDT machine infrastructure to automatically wire up the GIC and resolve interrupts defined in the Device Tree. Signed-off-by: Ruslan Ruslichenko <[email protected]> --- hw/intc/arm_gicv3.c | 45 +++++++++++++++++++++++++ hw/intc/arm_gicv3_common.c | 68 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 542f81ea49..e7e98ef9a5 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -18,9 +18,13 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" +#include "hw/core/cpu.h" +#include "hw/core/boards.h" #include "hw/intc/arm_gicv3.h" #include "gicv3_internal.h" +#include "hw/core/fdt_generic_util.h" + static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio, bool nmi) { /* Return true if this IRQ at this priority should take @@ -452,14 +456,55 @@ static void arm_gic_realize(DeviceState *dev, Error **errp) gicv3_init_cpuif(s); } +static void arm_gic_fdt_auto_parent(FDTGenericIntc *obj, Error **errp) +{ + GICv3State *s = ARM_GICV3(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + int num_cpus = s->num_cpu; + CPUState *cs; + int i = 0; + + for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { + if (i >= s->num_cpu) { + break; + } + + sysbus_connect_irq(sbd, i, + qdev_get_gpio_in(DEVICE(cs), 0)); + sysbus_connect_irq(sbd, i + num_cpus, + qdev_get_gpio_in(DEVICE(cs), 1)); + sysbus_connect_irq(sbd, i + 2 * num_cpus, + qdev_get_gpio_in(DEVICE(cs), 2)); + sysbus_connect_irq(sbd, i + 3 * num_cpus, + qdev_get_gpio_in(DEVICE(cs), 3)); + sysbus_connect_irq(sbd, i + 4 * num_cpus, + qdev_get_gpio_in(DEVICE(cs), 4)); + sysbus_connect_irq(sbd, i + 5 * num_cpus, + qdev_get_gpio_in(DEVICE(cs), 5)); + + if (s->maint_irq) { + int intbase = s->num_irq - GIC_INTERNAL + i * GIC_INTERNAL; + qemu_irq irq = qdev_get_gpio_in(DEVICE(sbd), + intbase + s->maint_irq); + qdev_connect_gpio_out_named(DEVICE(cs), + "gicv3-maintenance-interrupt", + 0, irq); + } + + i++; + } +} + static void arm_gicv3_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc = DEVICE_CLASS(klass); ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass); ARMGICv3Class *agc = ARM_GICV3_CLASS(klass); + FDTGenericIntcClass *fgic = FDT_GENERIC_INTC_CLASS(klass); agcc->post_load = arm_gicv3_post_load; device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize); + fgic->auto_parent = arm_gic_fdt_auto_parent; } static const TypeInfo arm_gicv3_info = { diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 9200671c7a..a393540825 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -34,6 +34,7 @@ #include "system/kvm.h" #include "system/whpx.h" +#include "hw/core/fdt_generic_util.h" static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs) { @@ -367,6 +368,69 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, } } +#define FDT_GENERIC_GICV3_TYPE_AFFINITY_ALL 0x01000000U +#define FDT_GENERIC_GICV3_TYPE_AFFINITY_IDX 0x02000000U + +static int arm_gicv3_common_fdt_get_irq(FDTGenericIntc *obj, qemu_irq *irqs, + uint32_t *cells, int ncells, int max, + Error **errp) +{ + GICv3State *gs = ARM_GICV3_COMMON(obj); + int cpu = 0; + uint32_t qemu_type; + uint32_t cpu_mask; + uint32_t idx; + + if (ncells != 3) { + error_setg(errp, "ARM GIC requires 3 interrupt cells, %d cells given", + ncells); + return 0; + } + idx = cells[1]; + qemu_type = cells[0] & 0xff000000; + + switch (cells[0] & 0x00ffffff) { + case 0: + if (idx >= gs->num_irq) { + error_setg(errp, "ARM GIC SPI has maximum index of %" PRId32 ", " + "index %" PRId32 " given", gs->num_irq - 1, idx); + return 0; + } + (*irqs) = qdev_get_gpio_in(DEVICE(obj), cells[1]); + return 1; + case 1: /* PPI */ + if (idx >= 16) { + error_setg(errp, "ARM GIC PPI has maximum index of 15, " + "index %" PRId32 " given", idx); + return 0; + } + if (qemu_type == FDT_GENERIC_GICV3_TYPE_AFFINITY_IDX) { + cpu = cells[2] >> 8; + *irqs = qdev_get_gpio_in(DEVICE(obj), + gs->num_irq - 16 + idx + cpu * 32); + return cpu; + } + + cpu_mask = cells[2] >> 8; + while ((cpu_mask || qemu_type == FDT_GENERIC_GICV3_TYPE_AFFINITY_ALL) + && cpu < max && cpu < gs->num_cpu) { + if ((cpu_mask & 1) || + qemu_type == FDT_GENERIC_GICV3_TYPE_AFFINITY_ALL) { + *irqs = qdev_get_gpio_in(DEVICE(obj), + gs->num_irq - 16 + idx + cpu * 32); + irqs++; + } + cpu_mask >>= 1; + cpu++; + } + return cpu; + default: + error_setg(errp, "Invalid cell 0 value in interrupt binding: %d", + cells[0]); + return 0; + } +} + static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) { GICv3State *s = ARM_GICV3_COMMON(dev); @@ -624,12 +688,15 @@ static void arm_gicv3_common_class_init(ObjectClass *klass, const void *data) DeviceClass *dc = DEVICE_CLASS(klass); ResettableClass *rc = RESETTABLE_CLASS(klass); ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass); + FDTGenericIntcClass *fgic = FDT_GENERIC_INTC_CLASS(klass); + rc->phases.hold = arm_gicv3_common_reset_hold; dc->realize = arm_gicv3_common_realize; device_class_set_props(dc, arm_gicv3_common_properties); dc->vmsd = &vmstate_gicv3; albifc->arm_linux_init = arm_gic_common_linux_init; + fgic->get_irq = arm_gicv3_common_fdt_get_irq; } static const TypeInfo arm_gicv3_common_type = { @@ -641,6 +708,7 @@ static const TypeInfo arm_gicv3_common_type = { .abstract = true, .interfaces = (const InterfaceInfo[]) { { TYPE_ARM_LINUX_BOOT_IF }, + { TYPE_FDT_GENERIC_INTC }, { }, }, }; -- 2.43.0
