In the GICv5 the handling mode of a PPI is not software configurable; it is reported via read-only CPU interface registers ICC_PPI_HMR0_EL1 and ICC_PPI_HMR1_EL1.
Signed-off-by: Peter Maydell <[email protected]> --- target/arm/cpu.h | 1 + target/arm/tcg/gicv5-cpuif.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index dd4dc12feb..4574f7005d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -605,6 +605,7 @@ typedef struct CPUArchState { uint64_t icc_icsr_el1; /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register */ uint64_t ppi_active[GICV5_NUM_PPIS / 64]; + uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; } gicv5_cpuif; struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 0132b13853..6fbc962131 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -50,6 +50,16 @@ FIELD(ICC_IDR0_EL1, GCIE_LEGACY, 8, 4) ((4 << R_ICC_IDR0_EL1_PRI_BITS_SHIFT) | \ (1 << R_ICC_IDR0_EL1_ID_BITS_SHIFT)) +/* + * PPI handling modes are fixed and not software configurable. + * R_CFSKX defines them for the architected PPIs: they are all Level, + * except that PPI 24 (CTIIRQ) is IMPDEF and PPI 3 (SW_PPI) is Edge. + * For unimplemented PPIs the field is RES0. The PPI register bits + * are 1 for Level and 0 for Edge. + */ +#define PPI_HMR0_RESET (~(1ULL << GICV5_PPI_SW_PPI)) +#define PPI_HMR1_RESET (~0ULL) + static GICv5Common *gicv5_get_gic(CPUARMState *env) { return env->gicv5state; @@ -292,6 +302,18 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[1]), .writefn = gic_ppi_sactive_write, }, + { .name = "ICC_PPI_HMR0_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 0, + .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_hm[0]), + .resetvalue = PPI_HMR0_RESET, + }, + { .name = "ICC_PPI_HMR1_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 1, + .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]), + .resetvalue = PPI_HMR1_RESET, + }, }; void define_gicv5_cpuif_regs(ARMCPU *cpu) -- 2.43.0
