These are the bits I needed to fix manually on top of what the model had done.
- ensure the SEV instruction is enabled for aa64 - remove the FEATURE_M check for aa32 - add an exit block so WFE can fall through On the last change I see the DISAS_WFI does tcg_gen_exit_tb to ensure we check for interrupts. However for yield and wfe we should just be able to roll into the next instruction. We could probably rationalise DISAS cases for all of these into a common handling. Signed-off-by: Alex Bennée <[email protected]> --- target/arm/tcg/a64.decode | 3 +-- target/arm/tcg/translate-a64.c | 10 ++++++++++ target/arm/tcg/translate.c | 4 +--- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 01b1b3e38be..d5b65d79da1 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -237,8 +237,7 @@ ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB YIELD 1101 0101 0000 0011 0010 0000 001 11111 WFE 1101 0101 0000 0011 0010 0000 010 11111 WFI 1101 0101 0000 0011 0010 0000 011 11111 - # We implement WFE to never block, so our SEV/SEVL are NOPs - # SEV 1101 0101 0000 0011 0010 0000 100 11111 + SEV 1101 0101 0000 0011 0010 0000 100 11111 # SEVL 1101 0101 0000 0011 0010 0000 101 11111 # Our DGL is a NOP because we don't merge memory accesses anyway. # DGL 1101 0101 0000 0011 0010 0000 110 11111 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index f76a00d1329..4714bedd01c 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2032,6 +2032,14 @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) return true; } +static bool trans_SEV(DisasContext *s, arg_SEV *a) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_sev(tcg_env); +#endif + return true; +} + static bool trans_WFE(DisasContext *s, arg_WFI *a) { /* @@ -10918,6 +10926,8 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) case DISAS_WFE: gen_a64_update_pc(dc, 4); gen_helper_wfe(tcg_env); + gen_goto_tb(dc, 1, 4); + /* tcg_gen_exit_tb(NULL, 0); */ break; case DISAS_YIELD: gen_a64_update_pc(dc, 4); diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index f9d1b8897d2..78ba7d2fde5 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -3248,9 +3248,7 @@ static bool trans_SEV(DisasContext *s, arg_SEV *a) * For system-mode M-profile, it sets the event register. */ #ifndef CONFIG_USER_ONLY - if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_helper_sev(tcg_env); - } + gen_helper_sev(tcg_env); #endif return true; } -- 2.47.3
