On Thu, Feb 19, 2026 at 08:19:30PM +0100, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé <[email protected]> > --- > target/riscv/gdbstub.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c > index f89b20ea84a..a053009ccd3 100644 > --- a/target/riscv/gdbstub.c > +++ b/target/riscv/gdbstub.c > @@ -52,7 +52,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray > *mem_buf, int n) > RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); > RISCVCPU *cpu = RISCV_CPU(cs); > CPURISCVState *env = &cpu->env; > - target_ulong tmp; > + uint64_t tmp; > > if (n < 32) { > tmp = env->gpr[n]; > @@ -80,7 +80,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t > *mem_buf, int n) > RISCVCPU *cpu = RISCV_CPU(cs); > CPURISCVState *env = &cpu->env; > int length = 0; > - target_ulong tmp; > + uint64_t tmp; > > switch (mcc->def->misa_mxl_max) { > case MXL_RV32: > @@ -194,7 +194,7 @@ static int riscv_gdb_set_csr(CPUState *cs, uint8_t > *mem_buf, int n) > const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8; > > if (n < CSR_TABLE_SIZE) { > - target_ulong val = ldn_p(mem_buf, regsz); > + uint64_t val = ldn_p(mem_buf, regsz); > int result; > > result = riscv_csrrw_debug(env, n, NULL, val, -1); > @@ -215,7 +215,7 @@ static int riscv_gdb_get_virtual(CPUState *cs, GByteArray > *buf, int n) > CPURISCVState *env = &cpu->env; > > /* Per RiscV debug spec v1.0.0 rc4 */ > - target_ulong vbit = (env->virt_enabled) ? BIT(2) : 0; > + uint32_t vbit = (env->virt_enabled) ? BIT(2) : 0; > > return gdb_get_regl(buf, env->priv | vbit); > #endif > -- > 2.52.0 > >
Reviewed-by: Chao Liu <[email protected]> Thanks, Chao
