Add new RISCV softmmu targets that define TARGET_BIG_ENDIAN=1 --- configs/targets/riscv32be-softmmu.mak | 8 ++++++++ configs/targets/riscv64be-softmmu.mak | 8 ++++++++ 2 files changed, 16 insertions(+) create mode 100644 configs/targets/riscv32be-softmmu.mak create mode 100644 configs/targets/riscv64be-softmmu.mak
diff --git a/configs/targets/riscv32be-softmmu.mak b/configs/targets/riscv32be-softmmu.mak new file mode 100644 index 0000000000..27c7467a43 --- /dev/null +++ b/configs/targets/riscv32be-softmmu.mak @@ -0,0 +1,8 @@ +TARGET_ARCH=riscv32 +TARGET_BASE_ARCH=riscv +TARGET_SUPPORTS_MTTCG=y +TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml +TARGET_NEED_FDT=y +TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=32 +TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y diff --git a/configs/targets/riscv64be-softmmu.mak b/configs/targets/riscv64be-softmmu.mak new file mode 100644 index 0000000000..528ecea2f8 --- /dev/null +++ b/configs/targets/riscv64be-softmmu.mak @@ -0,0 +1,8 @@ +TARGET_ARCH=riscv64 +TARGET_BASE_ARCH=riscv +TARGET_SUPPORTS_MTTCG=y +TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml +TARGET_NEED_FDT=y +TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=64 +TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y -- 2.34.1
