On 2/24/26 08:32, Jamin Lin wrote:
The current code updates the upper 32 bits of dma_dram_offset only when aic->has_dma64 is false, which is incorrect.If aic->has_dma64 is true, the controller supports 64-bit DMA addressing and the upper 32-bit DMA address register must be used to update the dma_dram_offset accordingly. Fix the condition so that the upper 32 bits are updated only when 64-bit DMA is supported. Fixes: efea7ddb4689a1ac4bce63a9ddb32887c7f3ac50 ("hw/i2c/aspeed_i2c: Fix DMA moving data into incorrect address") Signed-off-by: Jamin Lin <[email protected]> --- hw/i2c/aspeed_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 122bfdd63d..8022938f34 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -237,7 +237,7 @@ static void aspeed_i2c_set_tx_dma_dram_offset(AspeedI2CBus *bus) bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32, FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR)); - if (!aic->has_dma64) { + if (aic->has_dma64) { value = bus->regs[R_I2CM_DMA_TX_ADDR_HI]; bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 32, 32, @@ -262,7 +262,7 @@ static void aspeed_i2c_set_rx_dma_dram_offset(AspeedI2CBus *bus) bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32, FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR)); - if (!aic->has_dma64) { + if (aic->has_dma64) { value = bus->regs[R_I2CM_DMA_RX_ADDR_HI]; bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 32, 32,
Reviewed-by: Cédric Le Goater <[email protected]> Thanks, C.
