From: Weixie Cui <[email protected]> In xilinx_spips_reset() and xlnx_zynqmp_qspips_reset() a cut and paste error meant we reset the RX FIFO twice and the TX FIFO not at all. Correct this to reset both FIFOs.
Cc: [email protected] Signed-off-by: Weixie Cui <[email protected]> Reviewed-by: Thomas Huth <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-id: [email protected] [Rewrote commit message] Signed-off-by: Peter Maydell <[email protected]> --- hw/ssi/xilinx_spips.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index a4718fb72d..f6e717bc01 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -369,7 +369,7 @@ static void xilinx_spips_reset(DeviceState *d) memset(s->regs, 0, sizeof(s->regs)); fifo8_reset(&s->rx_fifo); - fifo8_reset(&s->rx_fifo); + fifo8_reset(&s->tx_fifo); /* non zero resets */ s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; @@ -397,7 +397,7 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d) memset(s->regs, 0, sizeof(s->regs)); fifo8_reset(&s->rx_fifo_g); - fifo8_reset(&s->rx_fifo_g); + fifo8_reset(&s->tx_fifo_g); fifo32_reset(&s->fifo_g); s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET; s->regs[R_GPIO] = 1; -- 2.43.0
