On Thu, 2023-04-27 at 19:39 +0200, ~lexbaileylowrisc wrote: > From: Emmanuel Blot <[email protected]> > > Follow vendor-device syntax used with other RISCV cores > > Signed-off-by: Emmanuel Blot <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > hw/riscv/opentitan.c | 2 +- > target/riscv/cpu-qom.h | 2 +- > target/riscv/cpu.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > index 309125e854..19cb35b351 100644 > --- a/hw/riscv/opentitan.c > +++ b/hw/riscv/opentitan.c > @@ -119,7 +119,7 @@ static void > opentitan_machine_class_init(ObjectClass *oc, const void *data) > mc->desc = "RISC-V Board compatible with OpenTitan"; > mc->init = opentitan_machine_init; > mc->max_cpus = 1; > - mc->default_cpu_type = TYPE_RISCV_CPU_IBEX; > + mc->default_cpu_type = TYPE_RISCV_CPU_LOWRISC_IBEX; > mc->default_ram_id = "riscv.lowrisc.ibex.ram"; > mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size; > } > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > index 30dcdcfaae..3a6394fd11 100644 > --- a/target/riscv/cpu-qom.h > +++ b/target/riscv/cpu-qom.h > @@ -42,7 +42,7 @@ > #define TYPE_RISCV_CPU_RVA22S64 > RISCV_CPU_TYPE_NAME("rva22s64") > #define TYPE_RISCV_CPU_RVA23U64 > RISCV_CPU_TYPE_NAME("rva23u64") > #define TYPE_RISCV_CPU_RVA23S64 > RISCV_CPU_TYPE_NAME("rva23s64") > -#define TYPE_RISCV_CPU_IBEX > RISCV_CPU_TYPE_NAME("lowrisc-ibex") > +#define TYPE_RISCV_CPU_LOWRISC_IBEX > RISCV_CPU_TYPE_NAME("lowrisc-ibex") > #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti- > c") > #define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive- > e") > #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive- > e31") > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index e56470a374..24a4c2fd3f 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -3043,7 +3043,7 @@ static const TypeInfo riscv_cpu_type_infos[] = > { > .misa_mxl_max = MXL_RV32, > ), > > - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_IBEX, TYPE_RISCV_VENDOR_CPU, > + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_LOWRISC_IBEX, > TYPE_RISCV_VENDOR_CPU, > .misa_mxl_max = MXL_RV32, > .misa_ext = RVI | RVM | RVC | RVU, > .priv_spec = PRIV_VERSION_1_12_0,
