On Wed, 2023-03-29 at 19:16 +0200, ~lexbaileylowrisc wrote: > From: Emmanuel Blot <[email protected]>
Why? Alistair > > Signed-off-by: Emmanuel Blot <[email protected]> > --- > target/riscv/ibex_csr.c | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/target/riscv/ibex_csr.c b/target/riscv/ibex_csr.c > index d62638bbfb..a6e815e782 100644 > --- a/target/riscv/ibex_csr.c > +++ b/target/riscv/ibex_csr.c > @@ -69,7 +69,37 @@ static RISCVException any(CPURISCVState *env, int > csrno) > return RISCV_EXCP_NONE; > } > > +static RISCVException read_mtvec(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + *val = env->mtvec; > + > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_mtvec(CPURISCVState *env, int csrno, > + target_ulong val, uintptr_t a) > +{ > + /* bits [1:0] encode mode; Ibex only supports 1 = vectored */ > + if ((val & 3u) != 1u) { > + qemu_log_mask(LOG_UNIMP, > + "CSR_MTVEC: reserved mode not supported 0x" > TARGET_FMT_lx "\n", > + val); > + /* WARL */ > + return RISCV_EXCP_NONE; > + } > + > + /* bits [7:2] are always 0, address should be aligned in 256 > bytes */ > + env->mtvec = val & ~0xFCu; > + > + return RISCV_EXCP_NONE; > +} > + > const RISCVCSR ibex_csr_list[] = { > + { > + .csrno = CSR_MTVEC, > + .csr_ops = { "mtvec", any, &read_mtvec, &write_mtvec }, > + }, > { > .csrno = CSR_CPUCTRLSTS, > .csr_ops = { "cpuctrlsts", any, &read_cpuctrlsts, > &write_cpuctrlsts },
