On Fri, 2026-02-20 at 15:02 +0000, ~lexbaileylowrisc wrote: > This is the start of efforts to contribute code from the lowRISC fork > of > QEMU to bring the QEMU support for OpenTitan machines in line with > Earl > Grey
Thanks for the patches! > 1.0 by adding a new machine called ot-earlgrey. This work was done by I think we should just use the existing OpenTitan machine instead of adding a new one > Emmanuel Blot and Loïc Lefort from Rivos, and various people at > lowRISC. > This patch set in particular adds the basic machine definition, Ibex- > related changes, and one of the peripherals required for it: the > alert > handler device. > > I previously emailed asking for advice on how to test our changes in > a > way that is acceptable upstream, and how best to submit such a large > set > of changes, > if anyone has more thoughts on that, please do reply to that email. > ( > https://lists.nongnu.org/archive/html/qemu-riscv/2026-02/msg00139.html > ) > There's lots more commits to come, I don't want to dump too much on > the > mailing list all at once. For now this is a small first step. > > This patch set should give a flavour of the style of what's to come, > and > I'm expecting there will be some changes required. We'd just like to > understand what will be needed to make this acceptable as soon as we > can > before we try to upstream lots more of these changes. I gave a bunch of comments and some of them will apply to the entire series. In general: - Commits need SoB lines and commit messages describing what is happening and why - The new machine code especially needs to be formatted to follow other QEMU machines. Starting with the existing opentitan machine will help with this - We don't want to add a lot of device specific custom helpers and infrastructure. You will need to reuse existing QEMU helpers. Again starting with the existing OT machine will help here as it's already setup this way > > In particular, most of our new peripheral blocks are currently in the > directory called hw/opentitan. In our fork we have about 60 blocks in > this directory, we have put them there to keep them organised as > opentitan-specific blocks. Is this a suitable place for them? would > you > prefer a different structure? Following the general QEMU structure would be the way to go here. So add blocks to existing directories. For some things it might make sense to have an opentitan directory though, if there is no where else for them. Alistair > > Thanks! > > Emmanuel Blot (10): > [ot] target/riscv: rename ibex hart as lowrisc-ibex > [ot] hw/char, hw/timer, hw/ssi: fix device definitions > [ot] hw/riscv: add helper for Ibex platforms > [ot] target/riscv: implement custom LowRisc Ibex CSRs > [ot] target/riscv: add custom mtvec CSR management > [ot] target/riscv, hw/riscv: add basic OpenTitan EarlGrey machine > [ot] target/riscv: add support for impl-defined initial PMP config > [ot] hw/riscv: ot_earlgrey: add HW PMP configuration > [ot] hw/riscv: add an IRQ wrapper > [ot] hw/riscv, hw/opentitan: add Opentitan Alert handler device > > Loïc Lefort (1): > [ot] hw/opentitan: add OpenTitan shadow register helpers > > MAINTAINERS | 21 +- > hmp-commands-info.hx | 12 + > hw/Kconfig | 3 + > hw/char/Kconfig | 3 + > hw/char/meson.build | 2 +- > hw/meson.build | 1 + > hw/opentitan/Kconfig | 4 + > hw/opentitan/meson.build | 3 + > hw/opentitan/ot_alert.c | 668 +++++++++++++++++++++++ > hw/opentitan/trace-events | 6 + > hw/opentitan/trace.h | 2 + > hw/riscv/Kconfig | 14 + > hw/riscv/ibex_common.c | 316 +++++++++++ > hw/riscv/meson.build | 2 + > hw/riscv/opentitan.c | 30 +- > hw/riscv/ot_earlgrey.c | 851 > ++++++++++++++++++++++++++++++ > hw/ssi/Kconfig | 4 + > hw/ssi/meson.build | 2 +- > hw/timer/Kconfig | 3 + > hw/timer/ibex_timer.c | 2 +- > hw/timer/meson.build | 2 +- > include/hw/opentitan/ot_alert.h | 23 + > include/hw/opentitan/ot_common.h | 93 ++++ > include/hw/riscv/ibex_common.h | 322 +++++++++++ > include/hw/riscv/ibex_irq.h | 69 +++ > include/hw/riscv/opentitan.h | 4 +- > include/hw/riscv/ot_earlgrey.h | 27 + > meson.build | 1 + > target/riscv/cpu-qom.h | 4 +- > target/riscv/cpu.c | 40 +- > target/riscv/cpu.h | 7 + > target/riscv/cpu_cfg_fields.h.inc | 7 + > target/riscv/ibex_csr.c | 115 ++++ > target/riscv/meson.build | 1 + > 34 files changed, 2641 insertions(+), 23 deletions(-) > create mode 100644 hw/opentitan/Kconfig > create mode 100644 hw/opentitan/meson.build > create mode 100644 hw/opentitan/ot_alert.c > create mode 100644 hw/opentitan/trace-events > create mode 100644 hw/opentitan/trace.h > create mode 100644 hw/riscv/ibex_common.c > create mode 100644 hw/riscv/ot_earlgrey.c > create mode 100644 include/hw/opentitan/ot_alert.h > create mode 100644 include/hw/opentitan/ot_common.h > create mode 100644 include/hw/riscv/ibex_common.h > create mode 100644 include/hw/riscv/ibex_irq.h > create mode 100644 include/hw/riscv/ot_earlgrey.h > create mode 100644 target/riscv/ibex_csr.c
