On Sat, Feb 21, 2026 at 06:02:21PM +0800, Tao Tang wrote: > The FIELD macro for the SMMU enable bit in the CR0 register was > incorrectly named SMMU_ENABLE. > > The ARM SMMUv3 Architecture Specification (both older IHI 0070.E.a and > newer IHI 0070.G.b) consistently refers to the SMMU enable bit as SMMUEN. > > This change makes our implementation consistent with the manual. > > Signed-off-by: Tao Tang <[email protected]> > Reviewed-by: Eric Auger <[email protected]> > Link: https://lists.nongnu.org/archive/html/qemu-arm/2025-09/msg01270.html
Same comment about fixes. Reviewed-by: Mostafa Saleh <[email protected]> Thanks, Mostafa > --- > hw/arm/smmuv3-internal.h | 2 +- > include/hw/arm/smmuv3-common.h | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index a6464425ec3..ebdb4ebae67 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -41,7 +41,7 @@ typedef enum SMMUTranslationClass { > > static inline int smmu_enabled(SMMUv3State *s) > { > - return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE); > + return FIELD_EX32(s->cr[0], CR0, SMMUEN); > } > > /* Command Queue Entry */ > diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h > index 2df54ba60f9..9f78bbe89eb 100644 > --- a/include/hw/arm/smmuv3-common.h > +++ b/include/hw/arm/smmuv3-common.h > @@ -351,7 +351,7 @@ REG32(IDR5, 0x14) > REG32(IIDR, 0x18) > REG32(AIDR, 0x1c) > REG32(CR0, 0x20) > - FIELD(CR0, SMMU_ENABLE, 0, 1) > + FIELD(CR0, SMMUEN, 0, 1) > FIELD(CR0, EVENTQEN, 2, 1) > FIELD(CR0, CMDQEN, 3, 1) > > -- > 2.34.1 >
