From: Brian Cain <[email protected]> The BADVA reg is referred to with the wrong identifier. The CAUSE reg field of SSR is not yet modeled, we will dump the SSR in a subsequent commit.
Signed-off-by: Brian Cain <[email protected]> --- target/hexagon/cpu.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 58a22ee41f2..82c726139f7 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -117,6 +117,14 @@ static void print_reg(FILE *f, CPUHexagonState *env, int regnum) hexagon_regnames[regnum], value); } +#ifndef CONFIG_USER_ONLY +static void print_sreg(FILE *f, CPUHexagonState *env, int regnum) +{ + qemu_fprintf(f, " %s = 0x" TARGET_FMT_lx "\n", + hexagon_sregnames[regnum], env->t_sreg[regnum]); +} +#endif + static void print_vreg(FILE *f, CPUHexagonState *env, int regnum, bool skip_if_zero) { @@ -216,8 +224,7 @@ static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags) qemu_fprintf(f, " cs0 = 0x00000000\n"); qemu_fprintf(f, " cs1 = 0x00000000\n"); #else - print_reg(f, env, HEX_REG_CAUSE); - print_reg(f, env, HEX_REG_BADVA); + print_sreg(f, env, HEX_SREG_BADVA); print_reg(f, env, HEX_REG_CS0); print_reg(f, env, HEX_REG_CS1); #endif -- 2.34.1
