On 2/27/26 19:56, Manos Pitsidianakis wrote:
@@ -1121,18 +1122,18 @@ static bool
hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar);
- /*
- * Disable SME, which is not properly handled by QEMU hvf yet.
- * To allow this through we would need to:
- * - make sure that the SME state is correctly handled in the
- * get_registers/put_registers functions
- * - get the SME-specific CPU properties to work with accelerators
- * other than TCG
- * - fix any assumptions we made that SME implies SVE (since
- * on the M4 there is SME but not SVE)
- */
- SET_IDREG(&host_isar, ID_AA64PFR1,
- GET_IDREG(&host_isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MASK);
+ if (hvf_arm_sme2_supported()) {
+ t = GET_IDREG(&host_isar, ID_AA64PFR1);
+ t = FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* FEAT_SME2 */
+ SET_IDREG(&host_isar, ID_AA64PFR1, t);
+
+ t = GET_IDREG(&host_isar, ID_AA64SMFR0);
+ t = FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 1); /* FEAT_SME2 */
+ SET_IDREG(&host_isar, ID_AA64SMFR0, t);
Why would you need to do this? Surely these values are already correct. And if they're
not, did we miss enabling something earlier?
This will break the moment FEAT_SME2p1 is supported.
r~
