On Mon, 2 Mar 2026, Chad Jablonski wrote:
Writing to any of the HOST_DATA0-7 registers pushes the written data
into a 128-bit accumulator. When the accumulator is full a flush is
triggered to copy it to the framebuffer. A final write to HOST_DATA_LAST
will also initiate a flush. The flush itself is left for the next patch.
Unaligned HOST_DATA* writes result in, from what I can tell, undefined
behavior on real hardware. A well-behaved driver shouldn't be doing this
anyway. For that reason they are not handled here at all.
Signed-off-by: Chad Jablonski <[email protected]>
---
hw/display/ati.c | 30 ++++++++++++++++++++++++++++++
hw/display/ati_dbg.c | 9 +++++++++
hw/display/ati_int.h | 9 +++++++++
hw/display/ati_regs.h | 9 +++++++++
4 files changed, 57 insertions(+)
diff --git a/hw/display/ati.c b/hw/display/ati.c
index 6cf243bcf9..965110c13a 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -1024,6 +1024,31 @@ static void ati_mm_write(void *opaque, hwaddr addr,
case SRC_SC_BOTTOM:
s->regs.src_sc_bottom = data & 0x3fff;
break;
+ case HOST_DATA0:
+ case HOST_DATA1:
+ case HOST_DATA2:
+ case HOST_DATA3:
+ case HOST_DATA4:
+ case HOST_DATA5:
+ case HOST_DATA6:
+ case HOST_DATA7:
+ if (!s->host_data.active) {
+ break;
+ }
+ s->host_data.acc[s->host_data.next++] = data;
+ if (s->host_data.next >= 4) {
+ qemu_log_mask(LOG_UNIMP, "HOST_DATA flush not yet implemented\n");
+ s->host_data.next = 0;
+ }
+ break;
+ case HOST_DATA_LAST:
+ if (!s->host_data.active) {
+ break;
+ }
+ s->host_data.acc[s->host_data.next] = data;
+ qemu_log_mask(LOG_UNIMP,
+ "HOST_DATA finish flush not yet implemented\n");
+ break;
These look quite similar so maybe it could be simpler as
case HOST_DATA7:
case HOST_DATA_LAST:
if (!s->host_data.active) {
break;
}
s->host_data.acc[s->host_data.next++] = data;
if (s->host_data.next >= 4 || addr == HOST_DATA_LAST) {
flush;
s->host_data.next = 0; // is this needed? flush might reset it
}
Regards,
BALATON Zoltan