On Wed, 4 Mar 2026, BALATON Zoltan wrote:
> On Mon, 2 Mar 2026, Chad Jablonski wrote:
>>>> +void ati_finish_host_data(ATIVGAState *s)
>>>> +{
>>>> + while (ati_flush_host_data(s)) {
>>>> + continue;
>>>> + }
>>>
>>> Is this while loop still needed? It looks like it will fill the rest of
>>> the blit rect with the last accumulator value instead of just finishing
>>> the blit in the middle. Is that what the real chip does? Otherwise this
>>> could just flush once and deactivate host data, couldn't it?
>>>
>>
>> This is how the real chip behaves, but it flushes the entire 256-bit
>> accumulator wrapping around until the blit is complete. Even though
>
> I think I now get how it may work but it's too late to try to model that for
> the next release and since the approach limited to 128 bits in v11 is simple
> enough and works well for what we need it so I think that's what we should
> include in the upcoming release. We may try to improve this in the future to
> better model the real chip but that may only really be needed when we make
> the 2D engine async which will be a bigger work so we can address this then.
>
> But before I forget I write it down now. I think there may actually be 8
> 32bit host data registers behind HOST_DATA0-HOST_DATA7 (that's 256 bits) but
> they are not accessed normally as registers but like a circular buffer or
> FIFO such as:
>
> reg 0 1 2 3 4 5 6 7
> wp ^ rp ^
This was broken by the mail client it was like this:
reg 0 1 2 3 4 5 6 7
wp ^
rp ^
Regards,
BALATON Zoltan
