On Wed, May 23, 2012 at 3:02 AM, Peter Maydell <peter.mayd...@linaro.org> wrote: > Make the state fields rx_desc_addr and tx_desc_addr uint32_t; > this matches the VMStateDescription, and also conforms to how > hardware works: the registers don't magically become larger > if the device is attached to a CPU with a larger physical > address size. It also fixes a compile failure if the > target_phys_addr_t type is changed to 64 bits. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Peter A. G. Crosthwaite <peter.crosthwa...@petalogix.com>
> --- > I'm going through fixing problems with moving target-arm to > a larger physical address width so we can support the A15 > Large Physical Address Extensions... > > hw/cadence_gem.c | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/cadence_gem.c b/hw/cadence_gem.c > index e2140ae..e563409 100644 > --- a/hw/cadence_gem.c > +++ b/hw/cadence_gem.c > @@ -339,8 +339,8 @@ typedef struct { > uint8_t phy_loop; /* Are we in phy loopback? */ > > /* The current DMA descriptor pointers */ > - target_phys_addr_t rx_desc_addr; > - target_phys_addr_t tx_desc_addr; > + uint32_t rx_desc_addr; > + uint32_t tx_desc_addr; > > } GemState; > > -- > 1.7.1 >