On Mon, 23 Feb 2026 17:01:13 +0000
Peter Maydell <[email protected]> wrote:
> Add code to the GICv5 skeleton which creates the QOM properties which
> the board or SoC can use to configure the GIC, and the validation
> code to check they are in range. Generally these correspond to
> fields in the IRS ID registers, and the properties are named
> correspondingly.
>
> Notable here is that unlike the GICv3 (which assumes its connected
> CPUs are the system's CPUs starting from 0), we define a QOM array
> property which is an array of pointers to the CPUs, and a QOM array
> property which is an array of integers telling the GIC what the
> IAFFID (interrupt affinity ID) for each CPU is; so a board or SoC
> which wants to connect multiple CPUs to this GICv5 would do something
> like:
>
> QList *cpulist = qlist_new(), *iaffidlist = qlist_new();
>
> for (int i = 0; i < ms->smp.cpus; i++) {
> qlist_append_link(cpulist, OBJECT(qemu_get_cpu(i)));
> qlist_append_int(iaffidlist, i);
> }
> qdev_prop_set_array(vms->gic, "cpus", cpulist);
> qdev_prop_set_array(vms->gic, "cpu-iaffids", iaffidlist);
>
> Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
