Add a shared emulation library for AArch64 load/store instructions that
cause ISV=0 data aborts under hardware virtualization, and wire it into
HVF (macOS) and WHPX (Windows).
When the Instruction Syndrome Valid bit is clear, the hypervisor cannot
determine the faulting instruction's target register or access size from
the syndrome alone. This previously hit an assert(isv) and killed the
VM. The library fetches and decodes the faulting instruction using a
decodetree-generated decoder, then emulates it directly against the vCPU
register file and memory.
The library uses its own a64-ldst.decode rather than sharing
target/arm/tcg/a64.decode — TCG's trans_* functions emit IR into a
translation block, while this library's execute directly. Decode
patterns are kept consistent with TCG's where possible; differences
are noted in the relevant commit messages.
Changes since v4:
- Rebased onto current master
- Add SPDX license identifier to new meson.build
- Resent as new top-level thread (Alex Bennée)
Changes since v3:
- Document decodetree pattern differences from TCG in commit
messages for patches 1/6 and 5/6.
Changes since v2:
- Inject synchronous external abort (matching kvm_inject_arm_sea()
syndrome) on unhandled instruction or memory error, instead of
silently advancing PC or returning an error.
- Fix WHPX advance_pc bug: error paths no longer advance PC.
- Add page-crossing guard in mem_read/mem_write to prevent partial
side effects from cpu_memory_rw_debug().
Changes since v1:
- Split monolithic patch into 6 incremental patches: framework, then
one patch per coherent instruction group (Peter)
- Removed per-backend callback ops; library uses CPUArchState directly
with cpu_memory_rw_debug() for memory access (Mohamed)
- Removed mock unit tests (Mohamed; kvm-unit-tests is the right
vehicle for decoder validation)
- Added architectural justification for separate decode file
Lucas Amaral (6):
target/arm/emulate: add ISV=0 emulation library with load/store
immediate
target/arm/emulate: add load/store register offset
target/arm/emulate: add load/store pair
target/arm/emulate: add load/store exclusive
target/arm/emulate: add atomic, compare-and-swap, and PAC load
target/arm/hvf,whpx: wire ISV=0 emulation for data aborts
target/arm/emulate/a64-ldst.decode | 293 +++++++++++
target/arm/emulate/arm_emulate.c | 758 +++++++++++++++++++++++++++++
target/arm/emulate/arm_emulate.h | 30 ++
target/arm/emulate/meson.build | 8 +
target/arm/hvf/hvf.c | 46 +-
target/arm/meson.build | 1 +
target/arm/whpx/whpx-all.c | 61 ++-
7 files changed, 1193 insertions(+), 4 deletions(-)
create mode 100644 target/arm/emulate/a64-ldst.decode
create mode 100644 target/arm/emulate/arm_emulate.c
create mode 100644 target/arm/emulate/arm_emulate.h
create mode 100644 target/arm/emulate/meson.build
--
2.52.0
