From: Nathan Chen <[email protected]> Document arm-smmuv3 properties for setting HW-acceleration, Range Invalidation, and Address Translation Services support, as well as setting Output Address size and Substream ID size.
Reviewed-by: Eric Auger <[email protected]> Signed-off-by: Nathan Chen <[email protected]> --- qemu-options.hx | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/qemu-options.hx b/qemu-options.hx index 69e5a874c1..0ba8322695 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1279,13 +1279,46 @@ SRST ``aw-bits=val`` (val between 32 and 64, default depends on machine) This decides the address width of the IOVA address space. -``-device arm-smmuv3,primary-bus=id`` +``-device arm-smmuv3,primary-bus=id[,option=...]`` This is only supported by ``-machine virt`` (ARM). ``primary-bus=id`` Accepts either the default root complex (pcie.0) or a pxb-pcie based root complex. + ``accel=on|off`` (default: off) + Enables guest to leverage host SMMUv3 features for acceleration. + Enabling accel configures the host SMMUv3 in nested mode to support + vfio-pci passthrough. + + ``ril=on|off`` (default: on) + Support for Range Invalidation, which allows the SMMUv3 driver to + invalidate TLB entries for a range of IOVAs at once instead of issuing + separate commands to invalidate each page. Must match with host SMMUv3 + Range Invalidation support. Only applicable when accel=on. Setting + 'auto' is currently not supported. + + ``ats=on|off`` (default: off) + Support for Address Translation Services, which enables PCIe devices to + cache address translations in their local TLB and reduce latency. Host + SMMUv3 must support ATS in order to enable this feature for the vIOMMU. + Only applicable when accel=on. Setting 'auto' is currently not + supported. + + ``oas=val`` (supported values are 44 and 48. default: 44) + Sets the Output Address Size in bits. The value set here must be less + than or equal to the host SMMUv3's supported OAS, so that the + intermediate physical addresses (IPA) consumed by host SMMU for stage-2 + translation do not exceed the host's max supported IPA size. + Only applicable when accel=on. Setting 'auto' is currently not + supported. + + ``ssidsize=val`` (val between 0 and 20. default: 0) + Sets the Substream ID size in bits. When set to a non-zero value, + PASID capability is advertised to the vIOMMU and accelerated use cases + such as Shared Virtual Addressing (SVA) are supported. Only applicable + when accel=on. Setting 'auto' is currently not supported. + ``-device amd-iommu[,option=...]`` Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU). Only available with ``-machine q35``, it supports the following options: -- 2.43.0
