On 17/03/26, Helge Deller wrote: > From: Helge Deller <[email protected]> > > I checked on a physical A500, C3700 and C8000 machine and all load their > 64-bit PDC (Firmware) at 0xfffffff0f0000000, independed if the CPU uses > 40 or 44 physical address bits. > For qemu we will do the same and load the 64-bit SeaBIOS-hppa at the > same address for our emulated machines. > > Signed-off-by: Helge Deller <[email protected]> > --- > target/hppa/mem_helper.c | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c > index a4b382069d..ffbad8acfd 100644 > --- a/target/hppa/mem_helper.c > +++ b/target/hppa/mem_helper.c > @@ -27,6 +27,7 @@ > #include "exec/target_page.h" > #include "exec/helper-proto.h" > #include "hw/core/cpu.h" > +#include "hw/hppa/hppa_hardware.h" > #include "trace.h" > > hwaddr hppa_abs_to_phys_pa1x(uint8_t phys_addr_bits, vaddr addr) > @@ -66,12 +67,13 @@ hwaddr hppa_abs_to_phys_pa2_w0(uint8_t phys_addr_bits, > vaddr addr) > /* > * PDC address space: > * Figures H-10 and H-11 of the parisc2.0 spec do not specify > - * where to map into the 64-bit PDC address space. > - * We map with an offset which equals the 32-bit address, which > - * is what can be seen on physical machines too. > + * where to map into the 64-bit PDC address space, but verification > + * on physical A500, C3700 and C8000 machines show that PDC is always > + * mapped at 0xfffffff0f0000000, independed if the CPU has 40 or 44 > + * physical bits. > */ > addr = (uint32_t)addr; > - addr |= -1ull << (phys_addr_bits - 4); > + addr |= ((uint64_t) FIRMWARE_HIGH) << 32; > } > return addr; > } > -- > 2.53.0 > >
Reviewed-by: Anton Johansson <[email protected]>
