Prefer the address_space_ld/st API over the legacy ld/st_phys() because it allow checking for bus access fault (although the modified code doesn't check that). There is no logical change.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/loongarch/cpu_helper.c | 13 +++++++++---- target/loongarch/tcg/tlb_helper.c | 10 +++++++--- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 60441687667..4b7743c4f28 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -7,6 +7,7 @@ */ #include "qemu/osdep.h" +#include "system/memory.h" #include "system/tcg.h" #include "cpu.h" #include "accel/tcg/cpu-mmu-index.h" @@ -145,6 +146,7 @@ static MemTxResult loongarch_cmpxchg_phys(CPUState *cs, hwaddr phys, TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, int access_type, int mmu_idx, int debug) { + const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; CPUState *cs = env_cpu(env); hwaddr index = 0, phys = 0; uint64_t palen_mask = loongarch_palen_mask(env); @@ -174,7 +176,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, /* get next level page directory */ index = (address >> dir_base) & ((1 << dir_width) - 1); phys = base | index << 3; - base = ldq_le_phys(cs->as, phys); + base = address_space_ldq_le(cs->as, phys, attrs, NULL); if (level) { if (FIELD_EX64(base, TLBENTRY, HUGE)) { /* base is a huge pte */ @@ -204,10 +206,13 @@ restart: context->pte_buddy[1 - index] = base + BIT_ULL(dir_base); base += (BIT_ULL(dir_base) & address); } else if (cpu_has_ptw(env)) { + uint64_t val; + index &= 1; context->pte_buddy[index] = base; - context->pte_buddy[1 - index] = ldq_le_phys(cs->as, - phys + 8 * (1 - 2 * index)); + val = address_space_ldq_le(cs->as, phys + 8 * (1 - 2 * index), + attrs, NULL); + context->pte_buddy[1 - index] = val; } context->ps = dir_base; @@ -239,7 +244,7 @@ restart: ret1 = loongarch_cmpxchg_phys(cs, phys, pte, base); /* PTE updated by other CPU, reload PTE entry */ if (ret1 == MEMTX_DECODE_ERROR) { - base = ldq_le_phys(cs->as, phys); + base = address_space_ldq_le(cs->as, phys, attrs, NULL); goto restart; } diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index c0fd8527fe9..892e0eb4738 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -20,6 +20,7 @@ #include "exec/log.h" #include "cpu-csr.h" #include "tcg/tcg_loongarch.h" +#include "system/memory.h" typedef bool (*tlb_match)(bool global, int asid, int tlb_asid); @@ -709,7 +710,7 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base, hwaddr index, phys; uint64_t palen_mask = loongarch_palen_mask(env); uint64_t dir_base, dir_width; - + uint64_t val; if (unlikely((level == 0) || (level > 4))) { qemu_log_mask(LOG_GUEST_ERROR, @@ -736,7 +737,9 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base, get_dir_base_width(env, &dir_base, &dir_width, level); index = (badvaddr >> dir_base) & ((1 << dir_width) - 1); phys = base | index << 3; - return ldq_le_phys(cs->as, phys) & palen_mask; + val = address_space_ldq_le(cs->as, phys, MEMTXATTRS_UNSPECIFIED, NULL); + + return val & palen_mask; } void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd, @@ -802,7 +805,8 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd, ptoffset0 = ptindex << 3; ptoffset1 = (ptindex + 1) << 3; phys = base | (odd ? ptoffset1 : ptoffset0); - pte_raw = ldq_le_phys(cs->as, phys); + pte_raw = address_space_ldq_le(cs->as, phys, + MEMTXATTRS_UNSPECIFIED, NULL); tmp0 = loongarch_sanitize_hw_pte(env, pte_raw); ps = ptbase; } -- 2.53.0
