On 3/19/2026 5:21 AM, Markus Armbruster wrote:
Nathan Chen<[email protected]> writes:
From: Nathan Chen<[email protected]>
Document arm-smmuv3 properties for setting HW-acceleration,
Range Invalidation, and Address Translation Services support, as
well as setting Output Address size and Substream ID size.
Reviewed-by: Eric Auger<[email protected]>
Tested-by: Eric Auger<[email protected]>
Reviewed-by: Shameer Kolothum<[email protected]>
Signed-off-by: Nathan Chen<[email protected]>
---
qemu-options.hx | 32 +++++++++++++++++++++++++++++++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index 69e5a874c1..f8da35513a 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1279,13 +1279,43 @@ SRST
``aw-bits=val`` (val between 32 and 64, default depends on machine)
This decides the address width of the IOVA address space.
-``-device arm-smmuv3,primary-bus=id``
+``-device arm-smmuv3,primary-bus=id[,option=...]``
This is only supported by ``-machine virt`` (ARM).
``primary-bus=id``
Accepts either the default root complex (pcie.0) or a
pxb-pcie based root complex.
+ ``accel=on|off`` (default: off)
+ Enables guest to leverage host SMMUv3 features for acceleration.
+ Enabling accel configures the host SMMUv3 in nested mode to support
+ vfio-pci passthrough.
+
+ The following options are available when accel=on.
What happens when you try to use them with accel=off?
QEMU will error out and prevent VM boot if accel=off while trying to set
these properties to a value different from the default.
For instance:
qemu-system-aarch64: -device
arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1,accel=off,ril=on,ssidsize=20,oas=48,ats=on:
ats can only be enabled if accel=on
Thanks,
Nathan
