On Thu, 19 Mar 2026 at 23:27, <[email protected]> wrote: > > From: Alistair Francis <[email protected]> > > The following changes since commit 5a68a3add61208aad34d47134fdcfd3f407d2ce4: > > Update version for v11.0.0-rc0 release (2026-03-18 15:56:51 +0000) > > are available in the Git repository at: > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20260320 > > for you to fetch changes up to 38937473da3ebdd89bbe6bbc3effc0b153ceb414: > > target/riscv: Fix scountovf CSR behavior in VS-mode and M-mode (2026-03-20 > 08:41:15 +1000) > > ---------------------------------------------------------------- > RISC-V PR for 11. > > * Fix integer overflow in cm_base calculation > * Fix null pointer dereference in cpu_set_exception_base > * Update Daniel Henrique Barboza's email > * Add Chao Liu as reviewer > * Set SiFive PDMA done bit upon completion > * Remove deprecated 'riscv, delegate' device-tree property > * Fix OCP FP8 E4M3 conversion issues > * Fix IOMMU instance_init allocations in instance_finalize > * Support Smpmpmt extension > * Fix SiFive UART spurious IRQ issue and misc updates > * Fix missing flags merge in probe_pages for cross-page accesses > * Fix page probe issues in vext_ldff > * Fix scountovf CSR behavior in VS-mode and M-mode > > ----------------------------------------------------------------
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/11.0 for any user-visible changes. -- PMM
