Rename target_get_monitor_def() as riscv_monitor_get_register_legacy() and register it as CPUClass::legacy_monitor_get_register() handler.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/riscv/internals.h | 3 +++ target/riscv/cpu.c | 1 + target/riscv/monitor.c | 4 +++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 460346dd6de..90225d322ff 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -245,4 +245,7 @@ static inline int insn_len(uint16_t first_word) return (first_word & 3) == 3 ? 4 : 2; } +int riscv_monitor_get_register_legacy(CPUState *cs, const char *name, + uint64_t *pval); + #endif diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8ac935ac06e..e73d15476a7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2750,6 +2750,7 @@ static void riscv_cpu_common_class_init(ObjectClass *c, const void *data) cc->get_arch_id = riscv_get_arch_id; #endif cc->gdb_arch_name = riscv_gdb_arch_name; + cc->legacy_monitor_get_register = riscv_monitor_get_register_legacy; #ifdef CONFIG_TCG cc->tcg_ops = &riscv_tcg_ops; #endif /* CONFIG_TCG */ diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 3f206b9fca5..1c90c779534 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -26,6 +26,7 @@ #include "monitor/monitor.h" #include "monitor/hmp.h" #include "system/memory.h" +#include "internals.h" #ifdef TARGET_RISCV64 #define PTE_HEADER_FIELDS "vaddr paddr "\ @@ -310,7 +311,8 @@ static bool reg_is_vreg(const char *name) return false; } -int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval) +int riscv_monitor_get_register_legacy(CPUState *cs, const char *name, + uint64_t *pval) { CPURISCVState *env = &RISCV_CPU(cs)->env; target_ulong val = 0; -- 2.53.0
