Hi Fengyuan,
On 2026/3/14 09:11, Fengyuan Yu wrote:
Signed-off-by: Fengyuan Yu <[email protected]>
---
MAINTAINERS | 6 +
tests/qtest/libqos/meson.build | 3 +
tests/qtest/libqos/qos-intel-iommu.c | 454 +++++++++++++++++++++++++++
tests/qtest/libqos/qos-intel-iommu.h | 191 +++++++++++
4 files changed, 654 insertions(+)
create mode 100644 tests/qtest/libqos/qos-intel-iommu.c
create mode 100644 tests/qtest/libqos/qos-intel-iommu.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 247799c817..876e00ff77 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -151,6 +151,9 @@ F: target/i386/meson.build
F: tools/i386/
F: tests/functional/i386/
F: tests/functional/x86_64/
+F: tests/qtest/intel-iommu-test.c
+F: tests/qtest/libqos/qos-intel-iommu*
+F: tests/qtest/iommu-intel-test.c
X86 VM file descriptor change on reset test
M: Ani Sinha <[email protected]>
@@ -4026,6 +4029,9 @@ F: hw/i386/intel_iommu_accel.*
F: include/hw/i386/intel_iommu.h
F: tests/functional/x86_64/test_intel_iommu.py
F: tests/qtest/intel-iommu-test.c
+F: tests/qtest/libqos/qos-intel-iommu*
+F: tests/qtest/iommu-intel-test.c
+
AMD-Vi Emulation
M: Alejandro Jimenez <[email protected]>
diff --git a/tests/qtest/libqos/meson.build b/tests/qtest/libqos/meson.build
index 4a69acad0d..96f2fc48b4 100644
--- a/tests/qtest/libqos/meson.build
+++ b/tests/qtest/libqos/meson.build
@@ -73,6 +73,9 @@ endif
if config_all_devices.has_key('CONFIG_RISCV_IOMMU')
libqos_srcs += files('riscv-iommu.c', 'qos-riscv-iommu.c')
endif
+if config_all_devices.has_key('CONFIG_VTD')
+ libqos_srcs += files('qos-intel-iommu.c')
+endif
if config_all_devices.has_key('CONFIG_TPCI200')
libqos_srcs += files('tpci200.c')
endif
diff --git a/tests/qtest/libqos/qos-intel-iommu.c
b/tests/qtest/libqos/qos-intel-iommu.c
new file mode 100644
index 0000000000..b1baf5ea7c
--- /dev/null
+++ b/tests/qtest/libqos/qos-intel-iommu.c
@@ -0,0 +1,454 @@
+/*
+ * QOS Intel IOMMU (VT-d) Module Implementation
+ *
+ * This module provides Intel IOMMU-specific helper functions for libqos tests.
+ *
+ * Copyright (c) 2026 Fengyuan Yu <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/i386/intel_iommu_internal.h"
+#include "tests/qtest/libqos/pci.h"
+#include "qos-iommu-testdev.h"
+#include "qos-intel-iommu.h"
+
+#define QVTD_AW_48BIT_ENCODING 2
+
+uint32_t qvtd_expected_dma_result(QVTDTestContext *ctx)
+{
+ return ctx->config.expected_result;
+}
+
+uint32_t qvtd_build_dma_attrs(void)
+{
+ /*
+ * VT-d obtains the Requester ID (Source ID) from PCI bus/devfn routing
+ * via pci_device_iommu_address_space(), not from DMA attributes.
+ *
+ * For scalable mode, QEMU maps MemTxAttrs.pid==0 to PCI_NO_PASID,
+ * then remaps PCI_NO_PASID to PASID_0 when root_scalable is set.
+ * So returning 0 here implicitly selects PASID=0, which matches
+ * the PASID entry we configure in qvtd_build_pasid_table_entry().
+ *
+ */
+ return 0;
+}
The comment is partially misleading.
The SID part is correct. But iommu-testdev does not program
MemTxAttrs.pid( only program .secure and .space now), so returning 0
here does not explicitly select PASID=0. PASID_0 is reached implicitly
via VT-d’s no-PASID handling fallback, not via DMA_ATTRS.
I think the comment should be clarified to reflect this. You may need
check whether the related logic runs as your expectations. Expanding the
DMA_ATTRS in iommu-testdev is open if you really need it.
Thanks,
Tao
