From: Blue Swirl <blauwir...@gmail.com> Add an explicit CPUPPCState parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl <blauwir...@gmail.com> Signed-off-by: Alexander Graf <ag...@suse.de> Signed-off-by: Andreas Färber <afaer...@suse.de> Signed-off-by: Alexander Graf <ag...@suse.de> --- target-ppc/Makefile.objs | 1 - target-ppc/helper.h | 18 +++++++++--------- target-ppc/misc_helper.c | 19 +++++++++---------- target-ppc/translate.c | 2 +- target-ppc/translate_init.c | 12 ++++++------ 5 files changed, 25 insertions(+), 27 deletions(-) diff --git a/target-ppc/Makefile.objs b/target-ppc/Makefile.objs index 3a444eb..8d4d16b 100644 --- a/target-ppc/Makefile.objs +++ b/target-ppc/Makefile.objs @@ -9,5 +9,4 @@ obj-y += mmu_helper.o obj-y += timebase_helper.o obj-y += misc_helper.o -$(obj)/misc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS) $(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 81fc40e..b7a157e 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -363,7 +363,7 @@ DEF_HELPER_2(msgclr, void, env, tl) #endif DEF_HELPER_4(dlmzb, tl, env, tl, tl, i32) -DEF_HELPER_FLAGS_1(clcs, TCG_CALL_CONST | TCG_CALL_PURE, tl, i32) +DEF_HELPER_FLAGS_2(clcs, TCG_CALL_CONST | TCG_CALL_PURE, tl, env, i32) #if !defined(CONFIG_USER_ONLY) DEF_HELPER_2(rac, tl, env, tl) #endif @@ -375,8 +375,8 @@ DEF_HELPER_3(divso, tl, env, tl, tl) DEF_HELPER_2(load_dcr, tl, env, tl); DEF_HELPER_3(store_dcr, void, env, tl, tl) -DEF_HELPER_1(load_dump_spr, void, i32) -DEF_HELPER_1(store_dump_spr, void, i32) +DEF_HELPER_2(load_dump_spr, void, env, i32) +DEF_HELPER_2(store_dump_spr, void, env, i32) DEF_HELPER_1(load_tbl, tl, env) DEF_HELPER_1(load_tbu, tl, env) DEF_HELPER_1(load_atbl, tl, env) @@ -385,10 +385,10 @@ DEF_HELPER_1(load_601_rtcl, tl, env) DEF_HELPER_1(load_601_rtcu, tl, env) #if !defined(CONFIG_USER_ONLY) #if defined(TARGET_PPC64) -DEF_HELPER_1(store_asr, void, tl) +DEF_HELPER_2(store_asr, void, env, tl) DEF_HELPER_1(load_purr, tl, env) #endif -DEF_HELPER_1(store_sdr1, void, tl) +DEF_HELPER_2(store_sdr1, void, env, tl) DEF_HELPER_2(store_tbl, void, env, tl) DEF_HELPER_2(store_tbu, void, env, tl) DEF_HELPER_2(store_atbl, void, env, tl) @@ -397,12 +397,12 @@ DEF_HELPER_2(store_601_rtcl, void, env, tl) DEF_HELPER_2(store_601_rtcu, void, env, tl) DEF_HELPER_1(load_decr, tl, env) DEF_HELPER_2(store_decr, void, env, tl) -DEF_HELPER_1(store_hid0_601, void, tl) -DEF_HELPER_2(store_403_pbr, void, i32, tl) +DEF_HELPER_2(store_hid0_601, void, env, tl) +DEF_HELPER_3(store_403_pbr, void, env, i32, tl) DEF_HELPER_1(load_40x_pit, tl, env) DEF_HELPER_2(store_40x_pit, void, env, tl) -DEF_HELPER_1(store_40x_dbcr0, void, tl) -DEF_HELPER_1(store_40x_sler, void, tl) +DEF_HELPER_2(store_40x_dbcr0, void, env, tl) +DEF_HELPER_2(store_40x_sler, void, env, tl) DEF_HELPER_2(store_booke_tcr, void, env, tl) DEF_HELPER_2(store_booke_tsr, void, env, tl) DEF_HELPER_3(store_ibatl, void, env, i32, tl) diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c index 67eab08..b194d19 100644 --- a/target-ppc/misc_helper.c +++ b/target-ppc/misc_helper.c @@ -17,38 +17,37 @@ * License along with this library; if not, see <http://www.gnu.org/licenses/>. */ #include "cpu.h" -#include "dyngen-exec.h" #include "helper.h" #include "helper_regs.h" /*****************************************************************************/ /* SPR accesses */ -void helper_load_dump_spr(uint32_t sprn) +void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn) { qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn, env->spr[sprn]); } -void helper_store_dump_spr(uint32_t sprn) +void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn) { qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn, env->spr[sprn]); } #if !defined(CONFIG_USER_ONLY) #if defined(TARGET_PPC64) -void helper_store_asr(target_ulong val) +void helper_store_asr(CPUPPCState *env, target_ulong val) { ppc_store_asr(env, val); } #endif -void helper_store_sdr1(target_ulong val) +void helper_store_sdr1(CPUPPCState *env, target_ulong val) { ppc_store_sdr1(env, val); } -void helper_store_hid0_601(target_ulong val) +void helper_store_hid0_601(CPUPPCState *env, target_ulong val) { target_ulong hid0; @@ -65,7 +64,7 @@ void helper_store_hid0_601(target_ulong val) env->spr[SPR_HID0] = (uint32_t)val; } -void helper_store_403_pbr(uint32_t num, target_ulong value) +void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) { if (likely(env->pb[num] != value)) { env->pb[num] = value; @@ -74,12 +73,12 @@ void helper_store_403_pbr(uint32_t num, target_ulong value) } } -void helper_store_40x_dbcr0(target_ulong val) +void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val) { store_40x_dbcr0(env, val); } -void helper_store_40x_sler(target_ulong val) +void helper_store_40x_sler(CPUPPCState *env, target_ulong val) { store_40x_sler(env, val); } @@ -87,7 +86,7 @@ void helper_store_40x_sler(target_ulong val) /*****************************************************************************/ /* PowerPC 601 specific instructions (POWER bridge) */ -target_ulong helper_clcs(uint32_t arg) +target_ulong helper_clcs(CPUPPCState *env, uint32_t arg) { switch (arg) { case 0x0CUL: diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 5eec4b0..bcc9933 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -4551,7 +4551,7 @@ static void gen_abso(DisasContext *ctx) static void gen_clcs(DisasContext *ctx) { TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); - gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0); + gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); tcg_temp_free_i32(t0); /* Rc=1 sets CR0 to an undefined state */ } diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index f3a8aa5..f6ac589 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -347,7 +347,7 @@ static void spr_write_dbatl_h (void *opaque, int sprn, int gprn) /* SDR1 */ static void spr_write_sdr1 (void *opaque, int sprn, int gprn) { - gen_helper_store_sdr1(cpu_gpr[gprn]); + gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); } /* 64 bits PowerPC specific SPRs */ @@ -373,7 +373,7 @@ static void spr_read_asr (void *opaque, int gprn, int sprn) static void spr_write_asr (void *opaque, int sprn, int gprn) { - gen_helper_store_asr(cpu_gpr[gprn]); + gen_helper_store_asr(cpu_env, cpu_gpr[gprn]); } #endif #endif @@ -405,7 +405,7 @@ static void spr_write_hid0_601 (void *opaque, int sprn, int gprn) { DisasContext *ctx = opaque; - gen_helper_store_hid0_601(cpu_gpr[gprn]); + gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); /* Must stop the translation as endianness may have changed */ gen_stop_exception(ctx); } @@ -449,14 +449,14 @@ static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn) { DisasContext *ctx = opaque; - gen_helper_store_40x_dbcr0(cpu_gpr[gprn]); + gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); /* We must stop translation as we may have rebooted */ gen_stop_exception(ctx); } static void spr_write_40x_sler (void *opaque, int sprn, int gprn) { - gen_helper_store_40x_sler(cpu_gpr[gprn]); + gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); } static void spr_write_booke_tcr (void *opaque, int sprn, int gprn) @@ -481,7 +481,7 @@ static void spr_read_403_pbr (void *opaque, int gprn, int sprn) static void spr_write_403_pbr (void *opaque, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); - gen_helper_store_403_pbr(t0, cpu_gpr[gprn]); + gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -- 1.6.0.2
