Can somebody explain this code sniplet from hw/sparc32_dma.c to me? Either it is some hidden threaded gem (in which case s->dmaregs need to be volatile at least), or some tests are a bit confused and any reasonably optimizing compiler will create code that apparently the author did not intend:
static void dma_set_irq(void *opaque, int irq, int level) { DMAState *s = opaque; if (level) { s->dmaregs[0] |= DMA_INTR; if (s->dmaregs[0] & DMA_INTREN) { trace_sparc32_dma_set_irq_raise(); qemu_irq_raise(s->irq); } } else { if (s->dmaregs[0] & DMA_INTR) { s->dmaregs[0] &= ~DMA_INTR; if (s->dmaregs[0] & DMA_INTREN) { trace_sparc32_dma_set_irq_lower(); qemu_irq_lower(s->irq); } } } } Thanks, Martin