In preparation of removing the translator_ld[uw,l,q]() methods, inline them for the MIPS target, expanding MO_TE by a runtime check on mo_endian(ctx).
Mechanical change using the following Coccinelle 'spatch' script: @@ expression env, db, pc; @@ ( - translator_lduw(env, db, pc) + translator_lduw_end(env, db, pc, mo_endian(ctx)) | - translator_ldl(env, db, pc) + translator_ldl_end(env, db, pc, mo_endian(ctx)) | - translator_ldq(env, db, pc) + translator_ldq_end(env, db, pc, mo_endian(ctx)) ) Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]> --- target/mips/tcg/translate.c | 12 ++++++++---- target/mips/tcg/micromips_translate.c.inc | 2 +- target/mips/tcg/mips16e_translate.c.inc | 6 ++++-- target/mips/tcg/nanomips_translate.c.inc | 5 +++-- 4 files changed, 16 insertions(+), 9 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index fff6390f5d4..54ed253a7d0 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15149,17 +15149,21 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) is_slot = ctx->hflags & MIPS_HFLAG_BMASK; if (ctx->insn_flags & ISA_NANOMIPS32) { - ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); + ctx->opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next, + mo_endian(ctx)); insn_bytes = decode_isa_nanomips(env, ctx); } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { - ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next); + ctx->opcode = translator_ldl_end(env, &ctx->base, ctx->base.pc_next, + mo_endian(ctx)); insn_bytes = 4; decode_opc(env, ctx); } else if (ctx->insn_flags & ASE_MICROMIPS) { - ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); + ctx->opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next, + mo_endian(ctx)); insn_bytes = decode_isa_micromips(env, ctx); } else if (ctx->insn_flags & ASE_MIPS16) { - ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); + ctx->opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next, + mo_endian(ctx)); insn_bytes = decode_ase_mips16e(env, ctx); } else { gen_reserved_instruction(ctx); diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index da2419792eb..07172a6c7fe 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -1629,7 +1629,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) uint32_t op, minor, minor2, mips32_op; uint32_t cond, fmt, cc; - insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); + insn = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2, mo_endian(ctx)); ctx->opcode = (ctx->opcode << 16) | insn; rt = (ctx->opcode >> 21) & 0x1f; diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index 97da3456ea5..beb5b04ea29 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -453,7 +453,8 @@ static void decode_i64_mips16(DisasContext *ctx, static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) { - int extend = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); + int extend = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2, + mo_endian(ctx)); int op, rx, ry, funct, sa; int16_t imm, offset; @@ -686,7 +687,8 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx) /* No delay slot, so just process as a normal instruction */ break; case M16_OPC_JAL: - offset = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); + offset = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2, + mo_endian(ctx)); offset = (((ctx->opcode & 0x1f) << 21) | ((ctx->opcode >> 5) & 0x1f) << 16 | offset) << 2; diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 9d4e0bee81f..4b0b01ba37a 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -3551,7 +3551,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) int offset; int imm; - insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); + insn = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2, mo_endian(ctx)); ctx->opcode = (ctx->opcode << 16) | insn; rt = extract32(ctx->opcode, 21, 5); @@ -3665,7 +3665,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) break; case NM_P48I: { - insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 4); + insn = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 4, + mo_endian(ctx)); target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16; switch (extract32(ctx->opcode, 16, 5)) { case NM_LI48: -- 2.53.0
