The CPU_FOREACH() macro, defined in "hw/core/cpu.h",
ends up calling QTAILQ_FOREACH_RCU() which always
assigns its iterator variable when entering the loop.
Remove the pointless and possibly misleading assignment.
Mechanical patch using the following coccinelle spatch:
@@
type T;
identifier e;
iterator FOREACH_MACRO =~ ".*_FOREACH.*";
statement S;
@@
- T *e = ...;
+ T *e;
... when != e
FOREACH_MACRO(e, ...) S
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Message-Id: <[email protected]>
---
target/mips/internal.h | 2 +-
hw/misc/mips_cpc.c | 4 ++--
target/mips/tcg/system/cp0_helper.c | 8 ++++----
target/mips/tcg/system/tlb_helper.c | 2 +-
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 2fd5ffa304a..23e1ada1852 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -280,7 +280,7 @@ static inline int mips_vpe_active(CPUMIPSState *env)
static inline int mips_vp_active(CPUMIPSState *env)
{
- CPUState *cs = first_cpu;
+ CPUState *cs;
/* Check if the VP disabled other VPs (which means the VP is enabled) */
if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c
index 9d9c8bf6ec8..9ce37514d5b 100644
--- a/hw/misc/mips_cpc.c
+++ b/hw/misc/mips_cpc.c
@@ -45,7 +45,7 @@ static void mips_cpu_reset_async_work(CPUState *cs,
run_on_cpu_data data)
static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
{
- CPUState *cs = first_cpu;
+ CPUState *cs;
CPU_FOREACH(cs) {
uint64_t i = 1ULL << cs->cpu_index;
@@ -63,7 +63,7 @@ static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
{
- CPUState *cs = first_cpu;
+ CPUState *cs;
CPU_FOREACH(cs) {
uint64_t i = 1ULL << cs->cpu_index;
diff --git a/target/mips/tcg/system/cp0_helper.c
b/target/mips/tcg/system/cp0_helper.c
index 8b83ba16399..ba6b487b751 100644
--- a/target/mips/tcg/system/cp0_helper.c
+++ b/target/mips/tcg/system/cp0_helper.c
@@ -1570,7 +1570,7 @@ target_ulong helper_dvpe(CPUMIPSState *env)
target_ulong prev = cpu->mvp->CP0_MVPControl;
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
- CPUState *cs = first_cpu;
+ CPUState *cs;
CPU_FOREACH(cs) {
MIPSCPU *other_cpu = MIPS_CPU(cs);
@@ -1590,7 +1590,7 @@ target_ulong helper_evpe(CPUMIPSState *env)
target_ulong prev = cpu->mvp->CP0_MVPControl;
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
- CPUState *cs = first_cpu;
+ CPUState *cs;
CPU_FOREACH(cs) {
MIPSCPU *other_cpu = MIPS_CPU(cs);
@@ -1613,7 +1613,7 @@ target_ulong helper_dvp(CPUMIPSState *env)
target_ulong prev = env->CP0_VPControl;
if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
- CPUState *cpu = first_cpu;
+ CPUState *cpu;
CPU_FOREACH(cpu) {
MIPSCPU *other_cpu = MIPS_CPU(cpu);
@@ -1632,7 +1632,7 @@ target_ulong helper_evp(CPUMIPSState *env)
target_ulong prev = env->CP0_VPControl;
if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
- CPUState *cpu = first_cpu;
+ CPUState *cpu;
CPU_FOREACH(cpu) {
MIPSCPU *other_cpu = MIPS_CPU(cpu);
diff --git a/target/mips/tcg/system/tlb_helper.c
b/target/mips/tcg/system/tlb_helper.c
index 45cbeb40a2d..c850ddd9650 100644
--- a/target/mips/tcg/system/tlb_helper.c
+++ b/target/mips/tcg/system/tlb_helper.c
@@ -346,7 +346,7 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg,
uint32_t type)
uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1);
uint8_t invMsgR = 0;
uint32_t invMsgMMid = env->CP0_MemoryMapID;
- CPUState *cpu = first_cpu;
+ CPUState *cpu;
#ifdef TARGET_MIPS64
invMsgR = extract64(arg, 62, 2);
--
2.53.0
