On 26/03/05 12:09AM, Saif Abrar wrote:
> Add a method to be invoked on QEMU reset.
> Also add CFG and PBL core-blocks reset logic using
> appropriate bits of PHB_PCIE_CRESET register.
>
> Tested by reading the reset value of a register.
>
> Signed-off-by: Saif Abrar <[email protected]>
> Reviewed-by: Cédric Le Goater <[email protected]>
> Reviewed-by: Michael S. Tsirkin <[email protected]>
> ---
> v3: Updates for coding guidelines.
> v2:
> - Using the ResettableClass.
> - Reset of the root complex registers done in pnv_phb_root_port_reset_hold().
>
> hw/pci-host/pnv_phb.c | 1 +
> hw/pci-host/pnv_phb4.c | 103 +++++++++++++++++++++++++++-
> include/hw/pci-host/pnv_phb4.h | 1 +
> include/hw/pci-host/pnv_phb4_regs.h | 16 ++++-
> tests/qtest/pnv-phb4-test.c | 28 +++++++-
> 5 files changed, 145 insertions(+), 4 deletions(-)
>
> diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
> index 0b556d1bf5..d4f452d7b2 100644
> --- a/hw/pci-host/pnv_phb.c
> +++ b/hw/pci-host/pnv_phb.c
> @@ -232,6 +232,7 @@ static void pnv_phb_root_port_reset_hold(Object *obj,
> ResetType type)
> pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
> pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);
> pci_config_set_interrupt_pin(conf, 0);
> + pnv_phb4_cfg_core_reset(d);
seems these are common steps for phb4/5 now, if that's the case, do you
think this small change makes sense ?
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index d4f452d7b2fe..0432466b249f 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -220,7 +220,7 @@ static void pnv_phb_root_port_reset_hold(Object *obj,
ResetType type)
return;
}
- /* PHB4 and later requires these extra reset steps */
+ /* PHB4/5 and later requires these extra reset steps */
pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
PCI_IO_RANGE_MASK & 0xff);
pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
> }
>
> <...snip...>
> +void pnv_phb4_cfg_core_reset(PCIDevice *d)
> +{
> + uint8_t *conf = d->config;
> + uint32_t exp_offset = get_exp_offset(d);
> +
> + pci_set_word(conf + PCI_COMMAND, PCI_COMMAND_SERR);
> + pci_set_word(conf + PCI_STATUS, PCI_STATUS_CAP_LIST);
> + pci_set_long(conf + PCI_CLASS_REVISION, 0x06040000);
> + pci_set_long(conf + PCI_CACHE_LINE_SIZE, BIT(16));
> + pci_set_word(conf + PCI_MEMORY_BASE, BIT(4));
> + pci_set_word(conf + PCI_PREF_MEMORY_BASE, BIT(0) | BIT(4));
> + pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, PCI_PREF_RANGE_TYPE_64);
Above 3 configs are set twice, in this function as well as the callee
Also, these were set to different values before this patch, such as
PCI_MEMORY_BASE being set to BIT(0) in 'pnv_phb_root_port_reset_hold'.
Can this cause any issues ?
Also, can you help me find which section in spec contains the sequence
for core/pbl core reset ?
> + pci_set_long(conf + PCI_CAPABILITY_LIST, BIT(6));
> + pci_set_long(conf + PCI_CAPABILITY_LIST, BIT(6));
nit: duplicates
> <...snip...>
> + pci_set_long(conf + PHB_DLF_ECAP, 0x1F410025);
> + pci_set_long(conf + PHB_DLF_CAP, 0x80000001);
> + pci_set_long(conf + P16_ECAP, 0x22410026);
> + pci_set_long(conf + P32_ECAP, 0x1002A);
> + pci_set_long(conf + P32_CAP, 0x103);
the current patch has lots of hardcoded values (above ones and below
this line too), does it make sense to have macros or ppc_bitmasks for
some of them ?
> +}
> +
> +static void pnv_phb4_pbl_core_reset(PnvPHB4 *phb)
> +{
> + /* Zero all registers initially */
> + for (int i = PHB_PBL_CONTROL ; i <= PHB_PBL_ERR1_STATUS_MASK ; i += 8) {
> + phb->regs[i >> 3] = 0x0;
> + }
> +
> + /* Set specific register values */
> + phb->regs[PHB_PBL_CONTROL >> 3] = 0xC009000000000000;
> + phb->regs[PHB_PBL_TIMEOUT_CTRL >> 3] = 0x2020000000000000;
> + phb->regs[PHB_PBL_NPTAG_ENABLE >> 3] = 0xFFFFFFFF00000000;
> + phb->regs[PHB_PBL_SYS_LINK_INIT >> 3] = 0x80088B4642473000;
> +}
> +
> <...snip...>
> @@ -72,8 +95,6 @@ static void phb_version_test(const void *data)
> /* PHB Version register bits [24:31] */
> ver = ver >> (63 - 31);
> g_assert_cmpuint(ver, ==, expected_ver);
> -
> - qtest_quit(qts);
qtest_quit is removed here, won't it cause issues where QTestState is
not terminated properly ?
Thanks,
- Aditya G
