nice functionality ! On 26/03/05 12:09AM, Saif Abrar wrote: > <...snip...> > + /* > + * DMA sync: make it look like it's complete, > + * clear write-only read/write start sync bits. > + */ > + case PHB_DMA_SYNC: > + val = PHB_DMA_SYNC_RD_COMPLETE | > + ~(PHB_DMA_SYNC_RD_START | PHB_DMA_SYNC_WR_START); > + return val; > + > + /* > + * PCI-E Stack registers
nit: s/Stack registers/System Config Register/ ? > + */ > + case PHB_PCIE_SCR: > + val |= PHB_PCIE_SCR_PLW_X16; /* RO bit */ > + break; > + > /* Link training always appears trained */ > <...snip...> > diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c > index 419f34987a..2078fab9a9 100644 > --- a/tests/qtest/pnv-phb4-test.c > +++ b/tests/qtest/pnv-phb4-test.c > @@ -73,7 +73,8 @@ static void phb4_sticky_rst_test(QTestState *qts) > * Sticky reset test of PHB_PBL_ERR_STATUS. > * > * Write all 1's to reg PHB_PBL_ERR_INJECT. > - * Updated value will be copied to reg PHB_PBL_ERR_STATUS. > + * RO-only bits will not be written and > + * updated value will be copied to reg PHB_PBL_ERR_STATUS. > * > * Reset PBL core by setting PHB_PCIE_CRESET_PBL in reg PHB_PCIE_CRESET. > * Verify the sticky bits are still set. > @@ -81,7 +82,59 @@ static void phb4_sticky_rst_test(QTestState *qts) > PHB4_XSCOM_WRITE(PHB_PBL_ERR_INJECT, PPC_BITMASK(0, 63)); > PHB4_XSCOM_WRITE(PHB_PCIE_CRESET, PHB_PCIE_CRESET_PBL); /*Reset*/ > val = PHB4_XSCOM_READ(PHB_PBL_ERR_STATUS); > - g_assert_cmpuint(val, ==, (PPC_BITMASK(0, 9) | PPC_BITMASK(12, 63))); > + g_assert_cmpuint(val, ==, 0xF00DFD8E00); instead of this hardcoded value, can it be PPC_BITMASKs as previously used ? - Aditya G
