On 5/9/26 21:13, James Hilliard wrote:
SAA is an Octeon+ instruction that atomically adds rt to the naturally
aligned 32-bit word at base and discards the old memory value.
Add an Octeon+ feature bit, enable it for Octeon68XX, and implement the
common SAA/SAAD translator with TCG atomic_fetch_add_i64. The MemOp
selects the word or doubleword transaction size.
Signed-off-by: James Hilliard <[email protected]>
---
Changes v2 -> v3:
- Split SAA out of the combined Octeon arithmetic and memory
instruction patch. (requested by Richard Henderson)
Changes v3 -> v4:
- Gate SAA/SAAD behind an Octeon+ feature bit. (reported by Richard
Henderson)
- Use the i64 TCG atomic add path for both word and doubleword sizes.
(suggested by Richard Henderson)
---
target/mips/cpu-defs.c.inc | 2 +-
target/mips/mips-defs.h | 1 +
target/mips/tcg/octeon.decode | 4 ++++
target/mips/tcg/octeon_translate.c | 19 +++++++++++++++++++
4 files changed, 25 insertions(+), 1 deletion(-)
I beg your pardon here. Given that we implement only Octeon68XX, which is Octeon3,
there's not really a need for new feature bits. For clarity, we could rename INSN_OCTEON
to INSN_OCTEON3, but that's not really necessary either.
Anyway,
Reviewed-by: Richard Henderson <[email protected]>
r~
