This series updates MIPS linux-user unaligned-access behavior and fills in missing Octeon user-mode instruction support used by existing Octeon binaries.
The first patches model the Linux/MIPS sysmips ABI pieces needed by linux-user, including MIPS_FLUSH_CACHE, MIPS_ATOMIC_SET, and the MIPS_FIXADE policy used to control unaligned scalar access fixups. User-mode unaligned scalar accesses default to software fixups and sysmips(MIPS_FIXADE) can toggle SIGBUS/BUS_ADRALN behavior. The Octeon patches add integer, indexed memory, atomic, multiplier, COP2 crypto, CHORD, and LLM support. The series also adds a small mips64/mips64el TCG guest test covering representative Octeon integer, multiplier, and COP2 selector paths. The final patch corrects the Octeon68XX CP1 feature bits and FCR defaults. Changes since v1: - Split BADDU/DMUL destination fixes into a separate patch. - Split the SEQ/SNE decode refactoring into a separate patch. - Moved Octeon multiplier state to uint64_t arrays and updated VMState. - Switched Octeon helper ABIs to i64/uint64_t where applicable. - Moved COP2 selector decode/support logic into octeon_translate.c. - Added in-tree TCG tests for mips64 and mips64el linux-user. - Used switch ranges and g_assert_not_reached() for SHA3/ZUC shared selector handling. - Dropped Octeon prefixes from generic Camellia helper routines. - Replaced the reflected GFM 64-bit carryless multiply loop with crypto/clmul.h. - Moved the Octeon68XX CP1 CPU-model correction to the end of the series. - Added migration coverage for Octeon COP2 crypto and LLM sparse state. Signed-off-by: James Hilliard <[email protected]> --- Changes in v5: - Added Richard Henderson's Reviewed-by tags for LBX, LHUX, LWUX, SAA, and SAAD, plus Acked-by tags for ZCB and ZCBT. - Dropped the separate Octeon+ feature bit; QEMU has a single Octeon CPU model today, so SAA/SAAD stay under the existing Octeon feature bucket. - Folded ZCBT into the ZCB decodetree entry with a selector comment. - Link to v4: https://lore.kernel.org/qemu-devel/20260509-mips-octeon-missing-insns-v2-v4-0-d669dcd05...@gmail.com Changes in v4: - Added Richard Henderson's Reviewed-by tags to the reviewed sysmips and Octeon translator cleanup patches. - Kept the Octeon3 MPL3-MPL5/P3-P5 high-lane multiplier state documented by Cavium SDK/toolchain sources. - Documented the Octeon3 two-source MTM/MTP forms and preserved the rt high-lane operands while legacy one-source encodings use rt == $zero. - Simplified SAA/SAAD translation to use the i64 TCG atomic add path for both word and doubleword sizes. - Marked SAA/SAAD as Octeon+ instructions and gated them behind a separate Octeon+ feature bit. - Simplified LA* translation to use i64 TCG atomic helpers for word and doubleword operations, with MO_SL selecting word result sign-extension. - Link to v3: https://lore.kernel.org/qemu-devel/20260508-mips-octeon-missing-insns-v2-v3-0-bcbec9635...@gmail.com Changes in v3: - Rebased on current qemu.git master. - Split sysmips support into separate MIPS_FLUSH_CACHE, MIPS_ATOMIC_SET, and MIPS_FIXADE patches. - Made MIPS_ATOMIC_SET always use the MIPS separate error-result register path for successful returns. - Removed redundant Octeon MIPS64 checks and target-long guards from the translator paths. - Removed zero-register fast paths where gen_store_gpr() already handles discarded writes. - Reworked SEQ/SNE decode and LA* translator helpers as requested. - Split the Octeon arithmetic/memory patch into narrower state, indexed load, SAA/SAAD, ZCB, multiplier, and test patches. - Switched Octeon multiplier limb accumulation to uadd64_overflow(). - Link to v2: https://lore.kernel.org/qemu-devel/20260421-mips-octeon-missing-insns-v2-v2-0-a0791df18...@gmail.com To: [email protected] Cc: Laurent Vivier <[email protected]> Cc: Helge Deller <[email protected]> Cc: Pierrick Bouvier <[email protected]> Cc: Philippe Mathieu-Daudé <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Aurelien Jarno <[email protected]> Cc: Aleksandar Rikalo <[email protected]> Cc: Huacai Chen <[email protected]> --- James Hilliard (32): linux-user/mips: implement sysmips(MIPS_FLUSH_CACHE) linux-user/mips: implement sysmips(MIPS_ATOMIC_SET) linux-user/mips, target/mips: honor MIPS_FIXADE for unaligned accesses target/mips: fix Octeon arithmetic destination handling target/mips: split Octeon SEQ/SNE decode target/mips: drop Octeon zero-register fast paths target/mips: add Octeon multiplier state target/mips: add Octeon LBX instruction target/mips: add Octeon LHUX instruction target/mips: add Octeon LWUX instruction target/mips: add Octeon SAA instruction target/mips: add Octeon SAAD instruction target/mips: add Octeon ZCB instruction target/mips: add Octeon ZCBT instruction target/mips: add Octeon MTM0 instruction target/mips: add Octeon MTP0 instruction target/mips: add Octeon MTP1 instruction target/mips: add Octeon MTP2 instruction target/mips: add Octeon MTM1 instruction target/mips: add Octeon MTM2 instruction target/mips: add Octeon VMULU instruction target/mips: add Octeon VMM0 instruction target/mips: add Octeon V3MULU instruction tests/tcg/mips: add Octeon instruction smoke test target/mips: add Octeon LA* atomic instructions target/mips: add Octeon COP2 crypto core support target/mips: add Octeon SMS4 crypto support target/mips: add Octeon SHA3 crypto support target/mips: add Octeon ZUC crypto support target/mips: add Octeon Camellia crypto support target/mips: add Octeon CHORD and LLM COP2 support target/mips: expose Octeon68XX floating-point support MAINTAINERS | 2 + linux-user/mips/cpu_loop.c | 5 + linux-user/mips/target_syscall.h | 3 + linux-user/mips64/target_syscall.h | 3 + linux-user/syscall.c | 56 + target/mips/cpu-defs.c.inc | 10 +- target/mips/cpu.c | 75 +- target/mips/cpu.h | 257 +++ target/mips/helper.h | 6 + target/mips/internal.h | 3 + target/mips/system/machine.c | 142 ++ target/mips/tcg/meson.build | 1 + target/mips/tcg/octeon.decode | 46 +- target/mips/tcg/octeon_crypto.c | 2479 +++++++++++++++++++++++++ target/mips/tcg/octeon_translate.c | 537 +++++- target/mips/tcg/op_helper.c | 100 + target/mips/tcg/translate.c | 23 +- target/mips/tcg/translate.h | 1 + tests/tcg/mips/Makefile.target | 11 + tests/tcg/mips/user/isa/octeon/octeon-insns.c | 216 +++ tests/tcg/mips64/Makefile.target | 20 + tests/tcg/mips64el/Makefile.target | 8 + 22 files changed, 3946 insertions(+), 58 deletions(-) --- base-commit: ee7eb612be8f8886d48c1d0c1f1c65e495138f83 change-id: 20260420-mips-octeon-missing-insns-v2-5e693770cf2c Best regards, -- James Hilliard <[email protected]>
