This series aims to improve redability and maintainibility of the the AMD IVRS building by introducing macros and packed structs which represents IVRS, IVHDs headers and IVHD device entries.
The goal is to land a maintainable baseline before adding AMD hardware-accelerated vIOMMU support in QEMU, where we will require multiple vIOMMUs attached to different pcie-pxb buses in order to serve set of passthrough devices. Please refer to AMD IOMMU spec [1] for more details about IVRS. [1] https://docs.amd.com/api/khub/documents/GD6kOXjzWsek8QUbn_qMvg/content Sairaj Kodilkar (8): tests/acpi: x86: Allow IVRS acpi table changes amd_iommu: update PA, GVA and VA size macros amd_iommu: Return empty efr for stub call acpi_build: Use IOMMU pci device to build IOMMU device ID acpi_build: Introduce necessary macros and structs for AMD IOMMU IVRS acpi_build: Build IVRS feature report using extended feature register acpi_build: Cleanup AMD IOMMU IVRS building tests/acpi: x86: update golden masters for IVRS hw/i386/acpi-build.c | 191 +++++++++++++++++++-------------------- hw/i386/acpi-build.h | 93 ++++++++++++++++++- hw/i386/amd_iommu-stub.c | 2 +- hw/i386/amd_iommu.c | 2 +- hw/i386/amd_iommu.h | 12 ++- 5 files changed, 195 insertions(+), 105 deletions(-) -- 2.34.1
