Decode the equality and inequality forms as explicit SEQ/SNE and SEQI/SNEI instructions rather than using shared generated SEQNE/SEQNEI entries.
The explicit decoder names match the architectural mnemonics, which makes the translator entry points and trace/debug output easier to correlate with the instruction set. Reviewed-by: Richard Henderson <[email protected]> Signed-off-by: James Hilliard <[email protected]> --- Changes v1 -> v2: - Split the SEQ/SNE decode cleanup out of the Octeon arithmetic instruction patch. (suggested by Philippe Mathieu-Daudé) Changes v2 -> v3: - Remove the decoded ne field now that the instructions are split. - Reuse @r3 for SEQ/SNE and pass the TCG condition into a shared translator helper. (suggested by Richard Henderson) --- target/mips/tcg/octeon.decode | 7 +++-- target/mips/tcg/octeon_translate.c | 52 ++++++++++++++++++++------------------ 2 files changed, 32 insertions(+), 27 deletions(-) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode index 102a05860d..a2bfd0751d 100644 --- a/target/mips/tcg/octeon.decode +++ b/target/mips/tcg/octeon.decode @@ -30,6 +30,7 @@ BBIT 11 set:1 . 10 rs:5 ..... offset:s16 p=%bbit_p # SNEI rt, rs, immediate @r3 ...... rs:5 rt:5 rd:5 ..... ...... +&cmpi rs rt imm %bitfield_p 0:1 6:5 @bitfield ...... rs:5 rt:5 lenm1:5 ..... ..... . p=%bitfield_p @@ -38,8 +39,10 @@ DMUL 011100 ..... ..... ..... 00000 000011 @r3 EXTS 011100 ..... ..... ..... ..... 11101 . @bitfield CINS 011100 ..... ..... ..... ..... 11001 . @bitfield POP 011100 rs:5 00000 rd:5 00000 10110 dw:1 -SEQNE 011100 rs:5 rt:5 rd:5 00000 10101 ne:1 -SEQNEI 011100 rs:5 rt:5 imm:s10 10111 ne:1 +SEQ 011100 ..... ..... ..... 00000 101010 @r3 +SNE 011100 ..... ..... ..... 00000 101011 @r3 +SEQI 011100 rs:5 rt:5 imm:s10 101110 &cmpi +SNEI 011100 rs:5 rt:5 imm:s10 101111 &cmpi &lx base index rd @lx ...... base:5 index:5 rd:5 ...... ..... &lx diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c index 4dd7626835..8e49e16b5a 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -121,52 +121,54 @@ static bool trans_POP(DisasContext *ctx, arg_POP *a) return true; } -static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a) +static bool do_seq_sne(DisasContext *ctx, const arg_decode_ext_octeon1 *a, + TCGCond cond) { TCGv_i64 t0, t1; - if (a->rd == 0) { - /* nop */ - return true; - } - t0 = tcg_temp_new_i64(); t1 = tcg_temp_new_i64(); gen_load_gpr(t0, a->rs); gen_load_gpr(t1, a->rt); - if (a->ne) { - tcg_gen_setcond_i64(TCG_COND_NE, cpu_gpr[a->rd], t1, t0); - } else { - tcg_gen_setcond_i64(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0); - } + tcg_gen_setcond_i64(cond, t0, t1, t0); + gen_store_gpr(t0, a->rd); return true; } -static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a) +static bool trans_SEQ(DisasContext *ctx, arg_SEQ *a) { - TCGv_i64 t0; + return do_seq_sne(ctx, a, TCG_COND_EQ); +} - if (a->rt == 0) { - /* nop */ - return true; - } +static bool trans_SNE(DisasContext *ctx, arg_SNE *a) +{ + return do_seq_sne(ctx, a, TCG_COND_NE); +} - t0 = tcg_temp_new_i64(); +static bool do_seqi_snei(DisasContext *ctx, const arg_cmpi *a, TCGCond cond) +{ + TCGv_i64 t0; + t0 = tcg_temp_new_i64(); gen_load_gpr(t0, a->rs); - /* Sign-extend to 64 bit value */ - target_ulong imm = a->imm; - if (a->ne) { - tcg_gen_setcondi_i64(TCG_COND_NE, cpu_gpr[a->rt], t0, imm); - } else { - tcg_gen_setcondi_i64(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm); - } + tcg_gen_setcondi_i64(cond, t0, t0, a->imm); + gen_store_gpr(t0, a->rt); return true; } +static bool trans_SEQI(DisasContext *ctx, arg_SEQI *a) +{ + return do_seqi_snei(ctx, a, TCG_COND_EQ); +} + +static bool trans_SNEI(DisasContext *ctx, arg_SNEI *a) +{ + return do_seqi_snei(ctx, a, TCG_COND_NE); +} + static bool trans_lx(DisasContext *ctx, arg_lx *a, MemOp mop) { gen_lx(ctx, a->rd, a->base, a->index, mop); -- 2.54.0
