On 5/11/26 13:22, James Hilliard wrote:
Add per-thread Octeon multiplier state for the MPL and P limb banks used
by the VMULU/VMM0/V3MULU instruction family.
Octeon3 extends the older MPL0-MPL2/P0-P2 state with high lanes
MPL3-MPL5/P3-P5, programmed by the two-source MTM/MTP forms. Represent
both banks as uint64_t arrays so the TC state matches the architected
64-bit limb layout used by Octeon68XX user-mode code.
Migrate the multiplier registers in an Octeon-only subsection so
non-Octeon CPU models do not grow migration state.
Signed-off-by: James Hilliard<[email protected]>
---
Changes v2 -> v3:
- Split the multiplier state out of the combined Octeon arithmetic and
memory instruction patch. (requested by Richard Henderson)
Changes v3 -> v4:
- Document and keep the Octeon3 MPL3-MPL5/P3-P5 high-lane state used by
the two-source MTM/MTP forms.
---
target/mips/cpu.h | 12 ++++++++++++
target/mips/system/machine.c | 33 +++++++++++++++++++++++++++++++++
2 files changed, 45 insertions(+)
Reviewed-by: Richard Henderson <[email protected]>
r~
