target/riscv: rdcycleh problem

[Antony Pavlov]

Hi!

I use qemu-system-riscv32 v11.0.0 for running this code:

    15258:    c80025f3    rdcycleh a1
    1525c:    c0002573    rdcycle  a0
    15260:    c80027f3    rdcycleh a5
    15264:    fef59ae3    bne      a1,a5,15258

The code is recommended by riscv specification for reading 64-bit
cycle counter on 32-bit system (see
https://docs.riscv.org/reference/isa/unpriv/counters.html#7-1-1-zicntr-extension-for-base-counters-and-timers
for details).

When running on qemu-system-riscv32 both the rdcycle and the rdcycleh
instructions read low 32-bit of the cycle counter so the branch
instruction always go to 15258.

This quick and dirty patch fixes my problem:

--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1389,8 +1389,11 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState
*env, target_ulong *val,
      */
     if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
         riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
-        *val = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx) -
+        uint64_t t;
+
+        t = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx) -
                                                     ctr_prev + ctr_val;
+        *val = extract64(t, start, length);
     } else {
         *val = ctr_val;
     }

Have you any suggestion?

-- 
Best regards,
  Antony Pavlov