Hi Shameer, On 5/12/26 11:41 AM, Shameer Kolothum Thodi wrote: > >> -----Original Message----- >> From: Eric Auger <[email protected]> >> Sent: 12 May 2026 07:39 >> To: Shameer Kolothum Thodi <[email protected]>; >> [email protected]; [email protected]; qemu- >> [email protected]; [email protected]; [email protected]; >> [email protected]; [email protected]; [email protected]; >> [email protected] >> Cc: [email protected]; [email protected]; [email protected]; >> [email protected]; [email protected]; [email protected]; >> [email protected] >> Subject: Re: [PATCH v4 03/17] target/arm/cpu-sysregs.h.inc: Update with >> automatic generation >> > [...] > >>>> +DEF(MPIDR_EL1, 3, 0, 0, 0, 5) >>> Do we need MPIDR_EL1 as well? Is this considered as a feature ID >>> register and is writable? I don't think so. >> MPIDR_EL1 is part of the ID regs range defined in the kernel doc >> >> op0 = 3, op1 = {0,1,3}, crn = 0, crm within [0, 7], op2 within [0, 7] >> >> That's why the python script extracts it. Effectively it is not writable yet. >> >> I can exclude it from the automatic generation but do we really need to? Any >> specific reason? > No specific reason. The only thing is it's not really a feature ID register > but > a topology register and is not writable now. I leave that to you.
noted. I leave it as is for now and we will decide upon further reviews. Thanks Eric > > Thanks, > Shameer >
