From: Alistair Francis <[email protected]> The RISC-V spec states that
""" For a given supported fractional LMUL setting, implementations must support SEW settings between SEWMIN and LMUL * ELEN, inclusive. """ We were previously checking VLEN, instead of ELEN, so let's update to check ELEN instead of VLEN for fractional scaling. Cc: [email protected] Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3196 Signed-off-by: Alistair Francis <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: LIU Zhiwei <[email protected]> Reviewed-by: Chao Liu <[email protected]> Reviewed-by: Max Chou <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> (cherry picked from commit 5dcc64828dc79c2426905db5fae885f6ccf93347) (Mjt: context fixup) Signed-off-by: Michael Tokarev <[email protected]> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 466fe4d10c..6c94fdcdb4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -45,18 +45,17 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, target_ulong reserved = s2 & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, xlen - 1 - R_VTYPE_RESERVED_SHIFT); - uint16_t vlen = cpu->cfg.vlenb << 3; int8_t lmul; if (vlmul & 4) { /* * Fractional LMUL, check: * - * VLEN * LMUL >= SEW - * VLEN >> (8 - lmul) >= sew - * (vlenb << 3) >> (8 - lmul) >= sew + * ELEN * LMUL >= SEW + * ELEN >> (8 - vlmul) >= sew */ - if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) { + if (vlmul == 4 || + (cpu->cfg.elen >> (8 - vlmul)) < sew) { vill = true; } } -- 2.47.3
