Re: [PATCH v6 6/6] target/riscv: Enable SMMPT extension

[Nutty.Liu]

On 5/11/2026 8:47 PM, LIU Zhiwei wrote:

This patch implements v0.3.4 SMMPT
specification(https://github.com/riscv/riscv-smmtt/releases/tag/v0.3.4).

Co-authored-by: Huang Tao <eric.hu...@linux.alibaba.com>
Co-authored-by: TANG Tiancheng <lyn...@linux.alibaba.com>
Signed-off-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Chao Liu <chao.liu.zev...@gmail.com>
Reviewed-by: Frank Chang <frank.ch...@sifive.com>

Reviewed-by: Nutty Liu <nutty....@hotmail.com>

Thanks,
Nutty

---
  target/riscv/cpu.c | 15 ++++++++++++++-
  1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index dd54c2fa1e..31e59cd081 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -226,8 +226,10 @@ const RISCVIsaExtData isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
      ISA_EXT_DATA_ENTRY(smpmpmt, PRIV_VERSION_1_12_0, ext_smpmpmt),
      ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm),
+    ISA_EXT_DATA_ENTRY(smmpt, PRIV_VERSION_1_13_0, ext_smmpt),
      ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_13_0, ext_smnpm),
      ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi),
+    ISA_EXT_DATA_ENTRY(smsdid, PRIV_VERSION_1_13_0, ext_smsdid),
      ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
      ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
      ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_13_0, ext_ssccfg),
@@ -1383,6 +1385,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {

/* These are experimental so mark with 'x-' */

  const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+    MULTI_EXT_CFG_BOOL("x-smmpt", ext_smmpt, false),
+    MULTI_EXT_CFG_BOOL("x-smsdid", ext_smsdid, false),
      MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),

{ },

@@ -2633,6 +2637,15 @@ static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED = {
      },
  };

+static RISCVCPUImpliedExtsRule SMMPT_IMPLIED = {

+    .ext = CPU_CFG_OFFSET(ext_smmpt),
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_smsdid),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
  RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
      &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
      &RVM_IMPLIED, &RVV_IMPLIED, NULL
@@ -2652,7 +2665,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] 
= {
      &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
      &ZVKS_IMPLIED,  &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED,
      &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED, &SSCTR_IMPLIED,
-    NULL
+    &SMMPT_IMPLIED, NULL
  };

static const Property riscv_cpu_properties[] = {