On Wed, May 13, 2026 at 12:13:25PM +1000, Alistair Francis wrote: > On Tue, May 12, 2026 at 7:47 PM Kuan-Wei Chiu <[email protected]> wrote: > > > > T-Head CPUs use custom CSRs for performance monitoring, specifically > > mcounterinten (0x7ca) and mcounterof (0x7cb). > > > > Since we don't implement these custom PMU registers yet, the system > > crashes with an illegal instruction trap when OpenSBI like this: > > > > system_opcode_insn: Failed to access CSR 0x7ca from M-mode > > sbi_trap_error: hart0: trap1: illegal instruction handler failed (error -1) > > > > Add simple read/write stubs for these two CSRs. By silently ignoring > > writes and returning 0 on reads, we prevent the fatal exceptions and > > allow to continue normally. > > Can you include a link to the documentation for the CSRs > Sure. I'll add the link in v2.
Regards, Kuan-Wei
