Hello, In this version minor changes were made in patch 2 and 4. No other changes were made.
Patches are based on alistair/riscv-to-apply.next @56bbd4f25c, plus Chao Liu's series "[PATCH v6 0/7] riscv: add initial sdext support" [1]. For convenience this series is available at this branch: https://gitlab.com/danielhb/qemu/-/tree/riscv-server-ref_v6 Changes from v5: - patch 2: changed CPU satp mode to sv48 - patch 6: added extra information about how the board will eventually support future spec revisions - v5 link: https://lore.kernel.org/qemu-devel/[email protected]/ Daniel Henrique Barboza (2): target/riscv/cpu.c: remove 'bare' condition for .profile docs: add riscv-server-ref.rst Fei Wu (2): target/riscv: Add server platform reference cpu hw/riscv: server platform reference machine configs/devices/riscv64-softmmu/default.mak | 1 + docs/system/riscv/riscv-server-ref.rst | 37 + docs/system/target-riscv.rst | 1 + hw/riscv/Kconfig | 15 + hw/riscv/meson.build | 1 + hw/riscv/server_platform_ref.c | 1371 +++++++++++++++++++ target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 12 +- 8 files changed, 1438 insertions(+), 1 deletion(-) create mode 100644 docs/system/riscv/riscv-server-ref.rst create mode 100644 hw/riscv/server_platform_ref.c -- 2.43.0
