Fix to 64 bits in size and as these are mapped to TCG globals, be careful with host endianness when allocating globals. Casts are added to logging expressions to retain the correct size for TARGET_RISCV32.
Signed-off-by: Anton Johansson <[email protected]> Reviewed-by: Pierrick Bouvier <[email protected]> Acked-by: Alistair Francis <[email protected]> --- target/riscv/cpu.h | 6 +++--- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 6 +++--- target/riscv/machine.c | 6 +++--- target/riscv/translate.c | 12 +++++++----- 5 files changed, 17 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d9771ef845..15c9f8b3a0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -225,9 +225,9 @@ struct CPUArchState { uint8_t vxsat; bool vill; - target_ulong pc; - target_ulong load_res; - target_ulong load_val; + uint64_t pc; + uint64_t load_res; + uint64_t load_val; /* Floating-Point state */ uint64_t fpr[32]; /* assume both F and D extensions */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f9b57914ee..27310a95d1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -569,7 +569,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); } #endif - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); + qemu_fprintf(f, " %s %" PRIx64 "\n", "pc ", env->pc); #ifndef CONFIG_USER_ONLY for (i = 0; i < ARRAY_SIZE(csr_ops); i++) { int csrno = i; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 17305e1bb7..6236f65ff8 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -2334,9 +2334,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "%s: hart:%"PRIu64", async:%d, cause:"TARGET_FMT_lx", " - "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", - __func__, env->mhartid, async, cause, env->pc, tval, - riscv_cpu_get_trap_name(cause, async)); + "epc:0x%"PRIx64", tval:0x"TARGET_FMT_lx", desc=%s\n", + __func__, env->mhartid, async, cause, env->pc, + tval, riscv_cpu_get_trap_name(cause, async)); mode = env->priv <= PRV_S && cause < 64 && (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PRV_M; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 440b09fc32..66ed3f6504 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -433,9 +433,9 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64), VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64), - VMSTATE_UINTTL(env.pc, RISCVCPU), - VMSTATE_UINTTL(env.load_res, RISCVCPU), - VMSTATE_UINTTL(env.load_val, RISCVCPU), + VMSTATE_UINT64(env.pc, RISCVCPU), + VMSTATE_UINT64(env.load_res, RISCVCPU), + VMSTATE_UINT64(env.load_val, RISCVCPU), VMSTATE_UINTTL(env.frm, RISCVCPU), VMSTATE_UINTTL(env.badaddr, RISCVCPU), VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4a557b4907..b444fde3ef 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1484,6 +1484,10 @@ void riscv_translate_init(void) /* 32 bits in size, no offset needed */ size_t vl_offset = offsetof(CPURISCVState, vl); size_t vstart_offset = offsetof(CPURISCVState, vstart); + /* 64 bits in size mapped to TCGv, needs offset */ + size_t pc_offset = offsetof(CPURISCVState, pc) + field_offset; + size_t res_offset = offsetof(CPURISCVState, load_res) + field_offset; + size_t val_offset = offsetof(CPURISCVState, load_val) + field_offset; for (i = 1; i < 32; i++) { cpu_gpr[i] = tcg_global_mem_new(tcg_env, @@ -1499,11 +1503,9 @@ void riscv_translate_init(void) offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); } - cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc"); + cpu_pc = tcg_global_mem_new(tcg_env, pc_offset, "pc"); cpu_vl = tcg_global_mem_new_i32(tcg_env, vl_offset, "vl"); cpu_vstart = tcg_global_mem_new_i32(tcg_env, vstart_offset, "vstart"); - load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res), - "load_res"); - load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val), - "load_val"); + load_res = tcg_global_mem_new(tcg_env, res_offset, "load_res"); + load_val = tcg_global_mem_new(tcg_env, val_offset, "load_val"); } -- 2.52.0
