Signed-off-by: Richard Henderson <[email protected]>
---
target/arm/tcg/helper-fp8-defs.h | 2 ++
target/arm/tcg/fp8_helper.c | 37 ++++++++++++++++++++++++++++++++
target/arm/tcg/translate-a64.c | 15 +++++++++++++
target/arm/tcg/a64.decode | 2 ++
4 files changed, 56 insertions(+)
diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h
index bbc8d69e28..6530d1a6da 100644
--- a/target/arm/tcg/helper-fp8-defs.h
+++ b/target/arm/tcg/helper-fp8-defs.h
@@ -14,3 +14,5 @@ DEF_HELPER_FLAGS_4(sme2_fcvt_hb, TCG_CALL_NO_RWG, void, ptr,
ptr, env, i32)
DEF_HELPER_FLAGS_4(sme2_fcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(sve2_bfcvtn_bh, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
+
+DEF_HELPER_FLAGS_5(gvec_fcvt_bh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env,
i32)
diff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c
index 8d01393ff9..95c37a037e 100644
--- a/target/arm/tcg/fp8_helper.c
+++ b/target/arm/tcg/fp8_helper.c
@@ -183,6 +183,13 @@ static uint8_t fcvt_b16_to_fp8(bfloat16 x,
fcvt_fp8_output_fn *f8fmt,
return f8fmt(&p, scale, saturate, s);
}
+static uint8_t fcvt_f16_to_fp8(float16 x, fcvt_fp8_output_fn *f8fmt,
+ int scale, bool saturate, float_status *s)
+{
+ FloatParts64 p = float16_unpack_canonical(x, s);
+ return f8fmt(&p, scale, saturate, s);
+}
+
void HELPER(advsimd_bfcvtl)(void *vd, void *vn, CPUARMState *env, uint32_t
desc)
{
FP8Context ctx = fp8_src_start(env, desc, 0x3f);
@@ -372,3 +379,33 @@ void HELPER(sve2_bfcvtn_bh)(void *vd, void *vn,
CPUARMState *env, uint32_t desc)
fp8_finish(env, &ctx);
}
+
+void HELPER(gvec_fcvt_bh)(void *vd, void *vn, void *vm,
+ CPUARMState *env, uint32_t desc)
+{
+ FP8Context ctx = fp8_dst_start(env, desc, true);
+ fcvt_fp8_output_fn *output_fmt = fcvt_fp8_output_fmt[ctx.f8fmt];
+ uint16_t *n = vn;
+ uint16_t *m = vm;
+ uint8_t *d = vd;
+ bool osc = FIELD_EX64(env->vfp.fpmr, FPMR, OSC);
+ size_t oprsz = simd_oprsz(desc);
+ size_t nelem = oprsz / 2;
+ ARMVectorReg scratch;
+
+ if (vd == vm) {
+ m = memcpy(&scratch, vm, oprsz);
+ }
+
+ for (size_t i = 0; i < nelem; ++i) {
+ d[H1(i)] = fcvt_f16_to_fp8(n[H2(i)], output_fmt,
+ ctx.scale, osc, &ctx.stat);
+ }
+ for (size_t i = 0; i < nelem; ++i) {
+ d[H1(i) + nelem] = fcvt_f16_to_fp8(m[H2(i)], output_fmt,
+ ctx.scale, osc, &ctx.stat);
+ }
+
+ fp8_finish(env, &ctx);
+ clear_tail(vd, oprsz, simd_maxsz(desc));
+}
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 565053a1a4..0927eb6516 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -6522,6 +6522,21 @@ static gen_helper_gvec_3_ptr * const f_vector_fscale[3]
= {
};
TRANS_FEAT(FSCALE, aa64_f8cvt, do_fp3_vector, a, 0, f_vector_fscale)
+static bool trans_FCVTN_bh(DisasContext *s, arg_qrrr_e *a)
+{
+ if (!dc_isar_feature(aa64_f8cvt, s)) {
+ return false;
+ }
+ if (fpmr_access_check(s) && fp_access_check(s)) {
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vec_full_reg_offset(s, a->rm),
+ tcg_env, a->q ? 16 : 8, vec_full_reg_size(s),
+ FPST_A64 << 2, gen_helper_gvec_fcvt_bh);
+ }
+ return true;
+}
+
static bool do_fmlal(DisasContext *s, arg_qrrr_e *a, bool is_s, bool is_2)
{
if (fp_access_check(s)) {
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 26d31d0a33..71456d44e1 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1201,6 +1201,8 @@ FAMIN 0.10 1110 1.1 ..... 11011 1 ..... .....
@qrrr_sd
FSCALE 0.10 1110 110 ..... 00111 1 ..... ..... @qrrr_h
FSCALE 0.10 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd
+FCVTN_bh 0.00 1110 010 ..... 11110 1 ..... ..... @qrrr_h
+
### Advanced SIMD scalar x indexed element
FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
--
2.43.0
