Re: [PATCH v7 15/35] target/mips: add Octeon MTM0 instruction

[Richard Henderson]

On 5/14/26 10:37, James Hilliard wrote:
+static void octeon_reset_mtm0_mpl_state(void)
+{
+    TCGv_i64 zero = tcg_constant_i64(0);
+
+    /*
+     * MTM0 defines MPL1 as zero; model the architecturally unpredictable
+     * MPL2/MPL4/MPL5 lanes as zero for deterministic emulation.
+     */
+    octeon_store_mpl(1, zero);
+    octeon_store_mpl(2, zero);
+    octeon_store_mpl(4, zero);
+    octeon_store_mpl(5, zero);
+}

Thanks for the CN71xx docs.  The fact that MPL1 is cleared with index 0 makes sense, for 
backward compatibility with CN5xxx.  It's tempting to set the others to 0xdeadbeef, but ok.


Reviewed-by: Richard Henderson <richard.hender...@linaro.org>

r~