On 5/14/26 10:37, James Hilliard wrote:
MTP0 loads the low Octeon3 partial-product pair from rs/rt into P[0]
and P[3] and sets P[1] to zero. Model the architecturally unpredictable
P[2], P[4], and P[5] lanes as zero for deterministic emulation.
Legacy single-source encodings have rt encoded as $zero, so the same
translator path also preserves the older Octeon behavior. Add the
translator storage path so subsequent VMULU/VMM0/V3MULU operations can
consume guest-managed partial products.
Signed-off-by: James Hilliard <[email protected]>
---
Changes v2 -> v3:
- Split MTP0 out of the combined Octeon arithmetic and memory
instruction patch. (requested by Richard Henderson)
Changes v3 -> v4:
- Keep the Octeon3 two-source rt high-lane operand and document that
legacy one-source MTP encodings use rt == $zero.
Changes v5 -> v6:
- Zero P1 and model P2/P4/P5 as zero after checking the CN71XX
register-state table and description.
---
target/mips/tcg/octeon.decode | 1 +
target/mips/tcg/octeon_translate.c | 28 ++++++++++++++++++++++++++++
2 files changed, 29 insertions(+)
Reviewed-by: Richard Henderson <[email protected]>
r~
