On Wed, May 13, 2026 at 1:06 PM <[email protected]> wrote: > > From: Frank Chang <[email protected]> > > It's possible that the transmit watermark level (txctrl.txcnt) is > updated when the user writes to txctrl register, which may decrease the > transmit watermark level to less than the number of entries in the > transmit FIFO. In such a case, the interrupt should be raised so we need to > call sifive_uart_update_irq() to check and update interrupt when txctrl > register is written. Otherwise, the interrupt will have to be delayed > until next TX FIFO transmission is processed. > > Suggested-by: Chao Liu <[email protected]> > Signed-off-by: Frank Chang <[email protected]> > Reviewed-by: Jim Shu <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > hw/char/sifive_uart.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c > index b4de662d616..b9bbaaef595 100644 > --- a/hw/char/sifive_uart.c > +++ b/hw/char/sifive_uart.c > @@ -213,6 +213,7 @@ sifive_uart_write(void *opaque, hwaddr addr, > if (SIFIVE_UART_TXEN(s->txctrl) && !fifo8_is_empty(&s->tx_fifo)) { > sifive_uart_trigger_tx_fifo(s); > } > + sifive_uart_update_irq(s); > return; > case SIFIVE_UART_RXCTRL: > s->rxctrl = val64; > -- > 2.43.0 > >
